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AgeCommit message (Expand)Author
2010-06-23inorder: record load/store trace dataKorey Sewell
2010-06-23inorder: update branch predictorKorey Sewell
2010-06-23inorder-stats: add instruction type statsKorey Sewell
2010-06-23inorder: stall signal handlingKorey Sewell
2010-06-23inorder: tick schedulingKorey Sewell
2010-06-23O3ThreadContext: When taking over from a previous context, only assert thatTimothy M. Jones
2010-06-14stats: get rid of the never-really-used event stuffNathan Binkert
2010-06-10ruby: get rid of the Map classNathan Binkert
2010-06-10ruby: get rid of Vector and use STLNathan Binkert
2010-06-03Minor remote GDB cleanup.Steve Reinhardt
2010-06-02ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.Gabe Black
2010-06-02ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.Ali Saidi
2010-06-02ARM: Implement ARM CPU interruptsAli Saidi
2010-06-02ARM: Move PC mode bits around so they can be used for exectraceAli Saidi
2010-06-02Simple CPU: Make the FloatRegs trace flag do something.Gabe Black
2010-06-02CPU: Reset fetch offset after a exceptionAli Saidi
2010-06-02ARM: Make the predecoder handle Thumb instructions.Gabe Black
2010-05-13BPRED: Fixed the treshold-bug in the tournament predictor.Maximilien Breughe
2010-04-15tick: rename Clock namespace to SimClockNathan Binkert
2010-04-10inorder: timing for inst forwardingKorey Sewell
2010-04-02ruby: get rid of gems_common/util.hh and .cc and use stuff in src/baseNathan Binkert
2010-04-02ruby: get "using namespace" out of headersNathan Binkert
2010-03-29style: cleanup the Ruby TesterNathan Binkert
2010-03-27m5: merge inorder updatesKorey Sewell
2010-03-27inorder: write-hints bug fixKorey Sewell
2010-03-25CPU: Added comments to address translation classes.Timothy M. Jones
2010-03-23cpu: get rid of uncached access "events"Steve Reinhardt
2010-03-23cpu: fix exec tracing memory corruption bugSteve Reinhardt
2010-03-22inorder: import name for addtl. bpred statsKorey Sewell
2010-03-22inorder: fix squash bug in branch predictorMaximilien Breughe
2010-03-22inorder: fix address list bugKorey Sewell
2010-03-21TimingSimpleCPU: Fixed uncacacheable request read bugBrad Beckmann
2010-03-10ruby: get rid of std-includes.hhNathan Binkert
2010-02-26cpu_models: get rid of cpu_models.py and move the stuff into SConsNathan Binkert
2010-02-20BaseDynInst: Preserve the faults returned from read and write.Timothy M. Jones
2010-02-12O3PCU: Split loads and stores that cross cache line boundaries.Timothy M. Jones
2010-02-12BaseDynInst: Make the TLB translation timing instead of atomic.Timothy M. Jones
2010-01-31inorder: double delete inst bugKorey Sewell
2010-01-31inorder: inst count mgmtKorey Sewell
2010-01-31inorder: implement split storesKorey Sewell
2010-01-31inorder: implement split loadsKorey Sewell
2010-01-31inorder: add activity statsKorey Sewell
2010-01-31inorder: object cleanup in destructorsKorey Sewell
2010-01-31inorder: user per-thread dummy insts/reqsKorey Sewell
2010-01-31inorder: add execution unit statsKorey Sewell
2010-01-31inorder: recvRetry bug fixKorey Sewell
2010-01-31inorder-stats: add prereq to basic statKorey Sewell
2010-01-31inorder: ctxt switch statsKorey Sewell
2010-01-31inorder: pipeline stage statsKorey Sewell
2010-01-31inorder: enforce stage bandwidthKorey Sewell
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