Age | Commit message (Collapse) | Author |
|
|
|
Force all non-default ports to provide a name and an
owner in the constructor.
|
|
Separate simulation of icache stalls and dat stalls.
|
|
|
|
|
|
|
|
--HG--
extra : convert_revision : e6cdffe953d56b96c76c7ff14d2dcc3de3ccfcc3
|
|
the problem
--HG--
extra : convert_revision : d9713228d934cf4a45114a972603b8bca2bd27d3
|
|
--HG--
extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
|
|
--HG--
extra : convert_revision : 3194bde4c624d118969bfbf92282539963a72245
|
|
This should help if somebody gets to the bug
fix before me (or someone else)...
--HG--
extra : convert_revision : 0ae64c58ef4f7b02996f31e9e9e6bfad344719e2
|
|
you are squashing from the current instruction # causing the thread exit.
--HG--
extra : convert_revision : ccbeece7dd1d5fee43f30ab19370908972113473
|
|
from the right point (#32 usually) instead of restarting at 0 and double-freeing.
Commented out assert line in free_list.hh that will check for when double-free condition
goes bad.
--HG--
extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
|
|
--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
|
|
multiple times if an instruction faults.
--HG--
extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
|
|
--HG--
extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
|
|
--HG--
extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
|
|
--HG--
extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
|
|
execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state.
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>
--HG--
extra : convert_revision : dafc16814383e8e8f8320845edf6ab2bcfed1e1d
|
|
where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us. We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A. This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.
--HG--
extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
|
|
--HG--
extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
|
|
--HG--
extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
|
|
standard switch and change some ifs to work with the default port since every port is now connected to something.
--HG--
extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
|
|
to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations.
--HG--
extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
|
|
--HG--
extra : convert_revision : 8ddde313f2249e1346fa51372a156f0d2ddc3b8f
|
|
--HG--
extra : convert_revision : 6a6a7d05f62d9d9868be0707e4dc186a5f7ecf7d
|
|
--HG--
extra : convert_revision : 35d073d1279947d943a0290832e09a5268dd0b76
|
|
--HG--
extra : convert_revision : a9cfd2829c4aec191f5f9ec6ce7b5d1dccc92af1
|
|
--HG--
extra : convert_revision : 5e89484b2ef21457ffba35ef959df999a28c5676
|
|
--HG--
extra : convert_revision : 16fb8d7f3fbc5f8f1fc3ed34427c3d90a3125ad0
|
|
--HG--
extra : convert_revision : 15c5995e3acf23a45c712891fd06ef273584f7e8
|
|
"setShadowSet", "CacheOp"
--HG--
extra : convert_revision : a9ae8a7e62c27c2db16fd3cfa7a7f0bf5f0bf8ea
|
|
--HG--
extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec
|
|
--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
|
|
--HG--
extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042
|
|
--HG--
extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
|
|
--HG--
extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec
|
|
This is necssary for fault handlers that branch to non-zero micro PCs.
--HG--
extra : convert_revision : c1cb4863d779a9f4a508d0b450e64fb7a985f264
|
|
--HG--
extra : convert_revision : a305cf9dcaca5ed3b97499a5e24c511f4416125a
|
|
--HG--
extra : convert_revision : f27bb96850e7fb0252fb1f47c3d0860705c32884
|
|
--HG--
extra : convert_revision : 0631c601f281bdd2a12ff0d0ae94576780115c2a
|
|
--HG--
extra : convert_revision : 9b7af59a11202a91409aad7c427b7749cd1d2f12
|
|
--HG--
extra : convert_revision : 4624ccd3f08818f4632881d6aca6d1cc343bbdcf
|
|
Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).
--HG--
extra : convert_revision : b347cc0108f23890e9b73b3ee96059f0cea96cf6
|
|
file with them all.
--HG--
extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
|
|
--HG--
extra : convert_revision : 7d898c6b6b13094fd05326eaa0b095a3ab132397
|
|
--HG--
extra : convert_revision : 6d025764682181b1f67df3b1d8d1d59099136df7
|
|
--HG--
extra : convert_revision : 1aa0e4569a7c10e6a395c2c951ac29275b5bcf59
|
|
--HG--
extra : convert_revision : 68f8ff778dbd28ade5070edf5a7d662e7bf0045a
|
|
--HG--
extra : convert_revision : bc47206acb683ebaaa31f57af79b4b8db64e4d31
|