Age | Commit message (Expand) | Author |
2010-07-22 | LSQ Unit: After deleting part of a split request, set it to NULL so that it | Timothy M. Jones |
2010-07-22 | O3CPU: Fix a bug where stores in the cpu where never marked as split. | Timothy M. Jones |
2010-07-22 | O3CPU: O3's tick event gets squashed when it is switched out. When repeatedly | Timothy M. Jones |
2010-06-28 | inorder: remove another debug stat | Korey Sewell |
2010-06-26 | inorder: remove debugging stat | Korey Sewell |
2010-06-25 | inorder: Return Address Stack bug | Korey Sewell |
2010-06-25 | inorder: resource scheduling backend | Korey Sewell |
2010-06-24 | inorder: cleanup virtual functions | Korey Sewell |
2010-06-24 | inorder: enforce 78-character rule | Korey Sewell |
2010-06-24 | inorder: exe_unit_stats for resolved branches | Korey Sewell |
2010-06-23 | inorder: squash from memory stall | Korey Sewell |
2010-06-23 | inorder: record load/store trace data | Korey Sewell |
2010-06-23 | inorder: update branch predictor | Korey Sewell |
2010-06-23 | inorder-stats: add instruction type stats | Korey Sewell |
2010-06-23 | inorder: stall signal handling | Korey Sewell |
2010-06-23 | inorder: tick scheduling | Korey Sewell |
2010-06-23 | O3ThreadContext: When taking over from a previous context, only assert that | Timothy M. Jones |
2010-06-14 | stats: get rid of the never-really-used event stuff | Nathan Binkert |
2010-06-10 | ruby: get rid of the Map class | Nathan Binkert |
2010-06-10 | ruby: get rid of Vector and use STL | Nathan Binkert |
2010-06-03 | Minor remote GDB cleanup. | Steve Reinhardt |
2010-06-02 | ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR. | Gabe Black |
2010-06-02 | ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements. | Ali Saidi |
2010-06-02 | ARM: Implement ARM CPU interrupts | Ali Saidi |
2010-06-02 | ARM: Move PC mode bits around so they can be used for exectrace | Ali Saidi |
2010-06-02 | Simple CPU: Make the FloatRegs trace flag do something. | Gabe Black |
2010-06-02 | CPU: Reset fetch offset after a exception | Ali Saidi |
2010-06-02 | ARM: Make the predecoder handle Thumb instructions. | Gabe Black |
2010-05-13 | BPRED: Fixed the treshold-bug in the tournament predictor. | Maximilien Breughe |
2010-04-15 | tick: rename Clock namespace to SimClock | Nathan Binkert |
2010-04-10 | inorder: timing for inst forwarding | Korey Sewell |
2010-04-02 | ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base | Nathan Binkert |
2010-04-02 | ruby: get "using namespace" out of headers | Nathan Binkert |
2010-03-29 | style: cleanup the Ruby Tester | Nathan Binkert |
2010-03-27 | m5: merge inorder updates | Korey Sewell |
2010-03-27 | inorder: write-hints bug fix | Korey Sewell |
2010-03-25 | CPU: Added comments to address translation classes. | Timothy M. Jones |
2010-03-23 | cpu: get rid of uncached access "events" | Steve Reinhardt |
2010-03-23 | cpu: fix exec tracing memory corruption bug | Steve Reinhardt |
2010-03-22 | inorder: import name for addtl. bpred stats | Korey Sewell |
2010-03-22 | inorder: fix squash bug in branch predictor | Maximilien Breughe |
2010-03-22 | inorder: fix address list bug | Korey Sewell |
2010-03-21 | TimingSimpleCPU: Fixed uncacacheable request read bug | Brad Beckmann |
2010-03-10 | ruby: get rid of std-includes.hh | Nathan Binkert |
2010-02-26 | cpu_models: get rid of cpu_models.py and move the stuff into SCons | Nathan Binkert |
2010-02-20 | BaseDynInst: Preserve the faults returned from read and write. | Timothy M. Jones |
2010-02-12 | O3PCU: Split loads and stores that cross cache line boundaries. | Timothy M. Jones |
2010-02-12 | BaseDynInst: Make the TLB translation timing instead of atomic. | Timothy M. Jones |
2010-01-31 | inorder: double delete inst bug | Korey Sewell |
2010-01-31 | inorder: inst count mgmt | Korey Sewell |