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2010-11-23X86: Loosen an assert for x86 and connect the APIC ports when caches are used.Gabe Black
2010-11-19SCons: Support building without an ISAAli Saidi
2010-11-18O3: Fix fp destination register flattening, and index offset adjusting.Gabe Black
This change makes O3 flatten floating point destination registers, and also fixes misc register flattening so that it's correctly repositioned relative to the resized regions for integer and floating point indices. It also fixes some overly long lines.
2010-11-15O3: Make O3 support variably lengthed instructions.Gabe Black
2010-11-15O3: reset architetural state by calling clear()Ali Saidi
2010-11-15CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.Giacomo Gabrielli
2010-11-15O3: prevent a squash when completeAcc() modifies misc reg through TC.Min Kyu Jeong
This happens on ARM instructions when they update the IT state bits. Code and associated comment was copied from execute() and initiateAcc() methods
2010-11-15SCons: Cleanup SCons output during compileAli Saidi
2010-11-15CPU: Fix bug when a split transaction is issued to a faster cacheAli Saidi
In the case of a split transaction and a cache that is faster than a CPU we could get two responses before next_tick expires. Add an event that is scheduled in this case and return false rather than asserting.
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi
This change modifies the way prefetches work. They are now like normal loads that don't writeback a register. Previously prefetches were supposed to call prefetch() on the exection context, so they executed with execute() methods instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs are blank, meaning that they get executed, but don't actually do anything. On Alpha dead cache copy code was removed and prefetches are now normal ops. They count as executed operations, but still don't do anything and IsMemRef is not longer set on them. On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch instructions. The timing simple CPU doesn't try to do anything special for prefetches now and they execute with the normal memory code path.
2010-11-08ARM: Make all ARM uops delayed commit.Ali Saidi
2010-11-08sim: Use forward declarations for ports.Ali Saidi
Virtual ports need TLB data which means anything touching a file in the arch directory rebuilds any file that includes system.hh which in everything.
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-24O3: Get rid of a bunch of commented out lines.Gabe Black
2010-10-04Alpha: Fix Alpha NumMiscArchRegs constant.Gabe Black
Also add asserts in O3's Scoreboard class to catch bad indexes.
2010-09-30CPU/Cache: Fix some errors exposed by valgrindAli Saidi
2010-09-20CPU: Fix O3 and possible InOrder segfaults in FS.Gabe Black
2010-09-14CPU: Trim unnecessary includes from some common files.Gabe Black
This reduces the scope of those includes and makes it less likely for there to be a dependency loop. This also moves the hashing functions associated with ExtMachInst objects to be with the ExtMachInst definitions and out of utility.hh.
2010-09-13CPU: Get rid of the now unnecessary getInst/setInst family of functions.Gabe Black
This code is no longer needed because of the preceeding change which adds a StaticInstPtr parameter to the fault's invoke method, obviating the only use for this pair of functions.
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
2010-09-10style: fix sorting of includes and whitespace in some filesNathan Binkert
2010-08-31CPU: Get rid of the unused ev5_trap function on the simple and checker CPUs.Gabe Black
2010-08-25memtest: fix/cleanup functional access testingSteve Reinhardt
Don't assert that the response packet is marked as a response since it won't always be so for functional accesses. Also cleanup code to refer to functional accesses rather than "probes" (old terminology), and mention in the DPRINTF which type of access we're doing.
2010-08-25CPU: Print out traces for faluting inst when the flag ExecFaulting is setAli Saidi
2010-08-25ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)Min Kyu Jeong
When decoding a srs instruction, invalid mode encoding returns invalid instruction. This can happen when garbage instructions are fetched from mispredicted path
2010-08-24testers: move testers to a new directoryBrad Beckmann
This patch moves the testers to a new subdirectory under src/cpu and includes the necessary fixes to work with latest m5 initialization patches. --HG-- rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript
2010-08-23ISA: Get rid of old, unused utility functions cluttering up the ISAs.Gabe Black
2010-08-23CPU: Make the constants for StaticInst flags visible outside the class.Gabe Black
2010-08-23O3: Skipping mem-order violation check for uncachable loads.Min Kyu Jeong
Uncachable load is not executed until it reaches the head of the ROB, hence cannot cause one.
2010-08-23ARM: Improve printing of uop disassembly.Min Kyu Jeong
2010-08-23CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflagMin Kyu Jeong
2010-08-23CPU: Make Exec trace to print predication result (if false) for memory ↵Min Kyu Jeong
instructions
2010-08-23ARM: mark msr/mrs instructions as SerializeBefore/AfterMin Kyu Jeong
Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR
2010-08-23O3: Handle loads when the destination is the PC.Min Kyu Jeong
For loads that PC is the destination, check if the load was mispredicted again when the value being loaded returns from memory
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false.
2010-08-23CPU: Set a default value when readBytes faults.Ali Saidi
This was being done in read(), but if readBytes was called directly it wouldn't happen. Also, instead of setting the memory blob being read to -1 which would (I believe) require using memset with -1 as a parameter, this now uses bzero. It's hoped that it's more specialized behavior will make it slightly faster.
2010-08-20ruby: Fixed minor bug in ruby test for setting the request typeBrad Beckmann
2010-08-20ruby: Resurrected Ruby's deterministic testsBrad Beckmann
Added the request series and invalidate deterministic tests as new cpu models and removed the no longer needed ruby tests --HG-- rename : configs/example/rubytest.py => configs/example/determ_test.py rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/DirectedGenerator.cc rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/DirectedGenerator.hh rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/InvalidateGenerator.cc rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/InvalidateGenerator.hh rename : src/cpu/rubytest/RubyTester.cc => src/cpu/directedtest/RubyDirectedTester.cc rename : src/cpu/rubytest/RubyTester.hh => src/cpu/directedtest/RubyDirectedTester.hh rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/SeriesRequestGenerator.cc rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/SeriesRequestGenerator.hh
2010-08-20memtest: Memtester support for DMABrad Beckmann
This patch adds DMA testing to the Memtester and is inherits many changes from Polina's old tester_dma_extension patch. Since Ruby does not work in atomic mode, the atomic mode options are removed.
2010-08-14Inorder: Fix compilation of m5.fast.Gabe Black
printMemData is only used in DPRINTFs. If those are removed by compiling m5.fast, that function is unused, gcc generates a warning, that gets turned into an error, and the build fails. This change surrounds the function definition with #if TRACING_ON so it only gets compiled in if the DPRINTFs do to.
2010-08-13Merge with head.Gabe Black
2010-08-13CPU: Add readBytes and writeBytes functions to the exec contexts.Gabe Black
2010-08-13InOrder: Clean up some DPRINTFs that print data sent to/from the cache.Gabe Black
2010-08-13CPU: Tidy up endianness handling for mmapped "IPR"s.Gabe Black
2010-08-12TimingSimpleCPU: fix NO_ACCESS memory op handlingJoel Hestness
When a request is NO_ACCESS (x86 CDA microinstruction), the memory op doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs to handle the case where the current status of the CPU is Running and not DcacheWaitResponse or DTBWaitResponse
2010-07-22LSQ Unit: After deleting part of a split request, set it to NULL so that itTimothy M. Jones
isn't accidentally deleted again later (causing a segmentation fault).
2010-07-22O3CPU: Fix a bug where stores in the cpu where never marked as split.Timothy M. Jones
2010-07-22O3CPU: O3's tick event gets squashed when it is switched out. When repeatedlyTimothy M. Jones
switching between O3 and another CPU, O3's tick event might still be scheduled in the event queue (as squashed). Therefore, check for a squashed tick event as well as a non-scheduled event when taking over from another CPU and deal with it accordingly.
2010-06-28inorder: remove another debug statKorey Sewell
2010-06-26inorder: remove debugging statKorey Sewell
m5 doesnt do stats specific to binary and this resource request stat is probably only useful for people who really know the ins/outs of the model anyway