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AgeCommit message (Expand)Author
2008-11-13CPU: Refactor read/write in the simple timing CPU.Gabe Black
2008-11-10O3CPU: Make the instcount debugging stuff per-cpu.Clint Smullen
2008-11-10mem: update stuff for changes to Packet and RequestNathan Binkert
2008-11-09CPU: Make unaligned accesses work in the timing simple CPU.Gabe Black
2008-11-09X86: Make the timing simple CPU handle variable length instructions.Gabe Black
2008-11-05Right now a single thread cpu 1 could get assigned context Id != 1, dependingLisa Hsu
2008-11-04get rid of all instances of readTid() and getThreadNum(). Unify and eliminateLisa Hsu
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-11-02Make it so that all thread contexts are registered with the System, even inLisa Hsu
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
2008-10-27CPU: The API change to EventWrapper did not get propagated to the entirety o...Clint Smullen
2008-10-23s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos inLisa Hsu
2008-10-21style: Use the correct m5 style for things relating to interrupts.Nathan Binkert
2008-10-20O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...Ali Saidi
2008-10-12CPU: Explain why some code is commented out.Gabe Black
2008-10-12X86: Make the MicroPC type 16 bit.Gabe Black
2008-10-12X86: Don't fetch in the simple CPU if you're in the ROM.Gabe Black
2008-10-12Get rid of old RegContext code.Gabe Black
2008-10-12CPU: Make the highest order bit in the micro pc determine if it's combination...Gabe Black
2008-10-12CPU: Create a microcode ROM object in the CPU which is defined by the ISA.Gabe Black
2008-10-12X86: Fix the ordering of special physical address ranges.Gabe Black
2008-10-12X86: Make APICs communicate through the memory system.Gabe Black
2008-10-12X86: Make the local APIC accessible through the memory system directly, and m...Gabe Black
2008-10-12Turn Interrupts objects into SimObjects. Also, move local APIC state into x86...Gabe Black
2008-10-12CPU: Eliminate the get_vec function.Gabe Black
2008-10-11CPU: Add a getInterruptController functionGabe Black
2008-10-11CPU: Eliminate the simPalCheck funciton.Gabe Black
2008-10-11CPU: Eliminate the hwrei function.Gabe Black
2008-10-09SimObjects: Clean up handling of C++ namespaces.Nathan Binkert
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-10-09O3: Generaize the O3 IMPL class so it isn't split out by ISA.Gabe Black
2008-10-09O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.Gabe Black
2008-10-09O3: Generalize the O3 CPU object so it isn't split out by ISA.Gabe Black
2008-10-09CPU: Fix where setMicroPC was being called instead of setNextMicroPC.Gabe Black
2008-09-27gcc: Add extra parens to quell warnings.Nathan Binkert
2008-09-26O3CPU: Fix thread writeback logic.Kevin Lim
2008-09-26O3CPU: Add a hack to ensure that nextPC is set correctly after syscalls.Kevin Lim
2008-09-22gcc: Version 4.3 is pretty anal about shadowing types, placate it.Nathan Binkert
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...Ali Saidi
2008-08-19CPU: Get rid of two more duplicated CPU params.Gabe Black
2008-08-18Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was ...Richard Strong
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2008-08-03sockets: Add a function to disable all listening sockets.Nathan Binkert
2008-07-15Use ReadResp instead of LoadLockedResp for LoadLockedReq responses.Steve Reinhardt
2008-07-01Remove delVirtPort() and make getVirtPort() only return cached version.Ali Saidi
2008-07-01Make the cached virtPort have a thread context so it can do everything that a...Ali Saidi
2008-07-01After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFra...Ali Saidi
2008-06-28Backed out changeset 94a7bb476fca: caused memory leak.Steve Reinhardt
2008-06-21Generate more useful error messages for unconnected ports.Steve Reinhardt
2008-06-18AtomicSimpleCPU: Separate data stalls from instruction stalls.Nathan Binkert