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src/cpu/o3/cpu.cc:
Updates to make sure the checker is compiled in if enabled and also to include it only when it's used.
--HG--
extra : convert_revision : c48ead5b2665dc858acd87c2ee99d39d80594a69
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The changes largely are fixing up the memory accesses to use ports/Requests/Packets, supporting the splitting off of instantiation of template classes, and handling some of the reorganization that happened.
OzoneCPU is untested for now but at least compiles. Fixes will be coming shortly.
SConstruct:
Remove OzoneSimpleCPU from list of CPUs.
src/cpu/SConscript:
Leave out OzoneSimpleCPU.
src/cpu/ozone/bpred_unit.cc:
Fixes to get OzoneCPU to compile.
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst.hh:
src/cpu/ozone/dyn_inst_impl.hh:
src/cpu/ozone/front_end.cc:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/ozone_impl.hh:
src/cpu/ozone/rename_table.cc:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
Fixes to get OzoneCPU back to compiling.
--HG--
extra : convert_revision : 90ffb397263bcf9fea3987317272c64f2b20f7e6
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--HG--
extra : convert_revision : 63d98aa8b6a694c285d95a2a57e1b3aaef4cee3b
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src/cpu/o3/alpha_dyn_inst_impl.hh:
Consolidate these calls into one.
src/cpu/o3/commit_impl.hh:
Include checker only if it's being used.
src/cpu/o3/fetch_impl.hh:
Do not deallocate request if it's a squashed response that was received.
src/cpu/o3/lsq_unit.hh:
Add in comment.
src/cpu/o3/lsq_unit_impl.hh:
Only include checker if it's being used.
--HG--
extra : convert_revision : aae0bf1e19baae90f1e61d41191548612bbb3be6
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--HG--
extra : convert_revision : 3ead18e42f4a536f2f868da07cb81a8940a7fa2f
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--HG--
extra : convert_revision : 65d978d638dd9a57a641ca52adcf2c0ef48edf1c
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src/cpu/o3/alpha_cpu.hh:
Fix #define in header.
util/rundiff:
Fix file comments to be more correct.
util/tracediff:
Update comments to be more correct.
--HG--
extra : convert_revision : a28030ce8979de3d9361191c6af23743460dc53e
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision : 037fe9ee54da7e11c2bd07388b9f79cda9abef4c
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SConstruct:
Remove check for Checker from this SConstruct
src/arch/SConscript:
Specific check if CheckerCPU is being used. Not the cleanest, but works for now.
src/cpu/SConscript:
Code to handle using the CheckerCPU a little better. Allows -c to be used normally.
--HG--
extra : convert_revision : 0a82f16db0f38e5ce114d08368477bd211331fa3
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makes it easier to be able to specify only certain CPU models.
src/cpu/SConscript:
Split off instantiations into separate CC files. This makes it easier to split them per CPU model.
src/cpu/base_dyn_inst_impl.hh:
Move instantations out of impl.hh file and into a cc file.
src/cpu/checker/cpu_impl.hh:
Move instantiations over to .cc files inside each CPU's directory. Makes it easier to only use what's actually included.
src/cpu/o3/bpred_unit.cc:
Pull Ozone instantiations out of this .cc file; put them into the ozone's CC file.
src/cpu/o3/checker_builder.cc:
Instantiate Checker for O3 CPU.
src/cpu/ozone/checker_builder.cc:
Instantiate Checker for Ozone CPU.
--HG--
rename : src/cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst_impl.hh
rename : src/cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : src/cpu/checker/o3_builder.cc => src/cpu/o3/checker_builder.cc
rename : src/cpu/checker/ozone_builder.cc => src/cpu/ozone/checker_builder.cc
extra : convert_revision : 4e5f928b165379c06d31071c544ea46cf0b8fa71
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--HG--
extra : convert_revision : 20120d34ad2ab28d9dd5ac2907b974c40e511e9e
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SConstruct:
Fix paths in comments and other minor comment edits.
src/cpu/SConscript:
Fix path in comment.
--HG--
extra : convert_revision : c02aa9cefd8c5ad791ad2f1653c1554a4aa8ffbd
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
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extra : convert_revision : 488b9a9965dd86ca73dc9e510e5b3122cbd357f9
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directory and into the normal cpu directory.
src/SConscript:
Split off FuncUnits from old FUPool so I'm not including encumbered code. This was all written by Steve Raasch so it's safe to include in the main tree.
src/cpu/o3/fu_pool.cc:
Include the func unit file that's not in the encumbered directory.
--HG--
extra : convert_revision : 9801c606961dd2d62dba190d13a76069992bf241
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describes the ExecContext interface that the ISA uses to access CPU state. Also #ifdef Erik's old copy code from the decoder so ExecContext doesn't need his two specific copy functions.
src/arch/alpha/isa/decoder.isa:
Surround Erik's old copy code with #ifdefs. This way the copy functions don't need to be included in the ExecContext (until somebody decides to add them back in).
--HG--
extra : convert_revision : 508ca387757a32bb616e5b4b07af17787a76970e
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src/cpu/checker/cpu.cc:
Add in comment.
src/cpu/cpuevent.hh:
Fix up comment.
src/cpu/o3/bpred_unit.cc:
Comment out Ozone instantiations.
src/cpu/o3/dep_graph.hh:
Include destructor.
--HG--
extra : convert_revision : 549454ed11bc2fa49a0627f7fb8f96d00a9be303
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pretty simple so they shouldn't cause any trouble.
First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.
Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled.
SConstruct:
Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled.
configs/test/test.py:
Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick.
src/base/traceflags.py:
Add in O3CPU trace flag.
src/cpu/SConscript:
Rename AlphaFullCPU to AlphaO3CPU.
Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU.
src/cpu/cpu_models.py:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model.
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/thread_state.hh:
src/python/m5/objects/AlphaO3CPU.py:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
Also #ifdef the checker code so it doesn't need to be included if it's not selected.
--HG--
rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc
rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc
rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py
extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a
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src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
Updates for checker. Output more informative messages on error. Rename some functions. Add in option to warn (and not exit) on load results being incorrect.
src/cpu/checker/cpu_builder.cc:
src/cpu/checker/o3_cpu_builder.cc:
Add in parameter to warn (and not exit) on load result errors.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
Renamed checker functin.
--HG--
extra : convert_revision : d7aa28b8462691d20600f97a7213e2acd91c5665
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(i.e. Sparc & MIPS)
Still need to add some code to fetch & commit stages
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
Add nextNPC read & set functions
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
Add nextNPC
--HG--
extra : convert_revision : 120677547d54091411399156bd066ce5baf785f7
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into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision : 9b5b1419e8e22bce16ed97fc02c2008ca0181afc
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src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
Minor code cleanup by putting several bools into a bitset instead.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
Changed around some things in BaseDynInst.
--HG--
extra : convert_revision : 1db363d69a863cc8744cc9f9ec542ade8472eb42
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src/cpu/o3/commit_impl.hh:
src/cpu/o3/fetch.hh:
Update stats comments.
src/cpu/o3/fetch_impl.hh:
Differentiate stats.
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
Update for stats.
src/cpu/o3/lsq.hh:
LSQ now has stats.
src/cpu/o3/lsq_impl.hh:
Register stats of all LSQ units.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
Add in stats.
--HG--
extra : convert_revision : 7672ecf3c02515b268c28d5a986af1432197654a
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into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision : 78ef94172884c2db0f591c54657b28be5be7f61c
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into zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision : 1a00a3970c6064cb59cd2f788094569fc431bf70
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--HG--
extra : convert_revision : 20649b0b9b9c496aae22c19926c1166c8c0cc821
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into zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision : 349dbc2a39eba7fa5019c811123a643a41fdc6ff
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isn't verifiable by the checker.
src/arch/alpha/isa/decoder.isa:
src/cpu/checker/cpu.cc:
Fixes for checker.
--HG--
extra : convert_revision : b0ec8f3c4a10453a567cd6691283fc498403795e
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src/cpu/o3/decode_impl.hh:
src/cpu/o3/rename_impl.hh:
Fix output message.
--HG--
extra : convert_revision : f226b84d0e15f275286b1ed078d341831370322b
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src/cpu/base_dyn_inst.cc:
Clean up some code and update.
src/cpu/base_dyn_inst.hh:
Clean up some code and update with more descriptive function names.
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
Remove unused parameters.
src/cpu/o3/commit_impl.hh:
Remove unused parameters, also set squashCounter directly to the counted number of squashes.
src/cpu/o3/fetch_impl.hh:
Update for function name changes.
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
Remove unused parameter, move some code into a function.
--HG--
extra : convert_revision : 45abd77ad43dde2e93c2e53c4738c90ba8352a1d
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into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision : 7ac7b9c9288e4940899766cd2dd55ef793d48d4d
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src/arch/alpha/linux/system.cc:
src/cpu/o3/alpha_cpu_impl.hh:
src/sim/system.cc:
Merge fixes.
--HG--
extra : convert_revision : aa3326c0ebf54da9ab1dbd2d9877da41ca487082
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interface for external, non-CPU objects to access the thread, so they probably shouldn't be able to call syscall(). The case it was being used for was already handled by the ISA code.
src/arch/sparc/faults.cc:
src/cpu/thread_context.hh:
Fix for merge problems.
--HG--
extra : convert_revision : 05a7a2d6e45099fcf36d113da2e52450d892a72c
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into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision : 18a381fa230f2ef6d027359ffd619e3ae75cd446
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into iceaxe.:/Volumes/work/research/m5/merge
src/cpu/simple/base.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/python/m5/objects/System.py:
src/sim/system.cc:
src/sim/system.hh:
hand merge
--HG--
rename : build/SConstruct => SConstruct
rename : SConscript => src/SConscript
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/linux/system.hh => src/arch/alpha/linux/system.hh
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : base/statistics.cc => src/base/statistics.cc
rename : base/statistics.hh => src/base/statistics.hh
rename : base/stats/mysql.cc => src/base/stats/mysql.cc
rename : base/stats/mysql.hh => src/base/stats/mysql.hh
rename : base/stats/statdb.cc => src/base/stats/statdb.cc
rename : base/stats/statdb.hh => src/base/stats/statdb.hh
rename : base/stats/text.cc => src/base/stats/text.cc
rename : base/stats/text.hh => src/base/stats/text.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : kern/kernel_stats.cc => src/kern/kernel_stats.cc
rename : kern/kernel_stats.hh => src/kern/kernel_stats.hh
rename : kern/system_events.cc => src/kern/system_events.cc
rename : kern/system_events.hh => src/kern/system_events.hh
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/system.cc => src/sim/system.cc
rename : sim/system.hh => src/sim/system.hh
rename : test/stattest.cc => src/unittest/stattest.cc
extra : convert_revision : 4bb576a2bf5e32784efc48030bd776c6c7c29a7c
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- change include from exec_context.hh -> threadcontext.hh
- g++ 4.0.3 complaint about broken code (which it was).
- bad merge thread_context -> exec_context
src/arch/sparc/isa/includes.isa:
Fix SPARC_SE for exec_context->thread_context switch
src/arch/sparc/regfile.hh:
fix g++ 4.0.3 complaint about broken code (which it was).
src/cpu/thread_context.hh:
fix bad merge
--HG--
extra : convert_revision : f5bab822d5c25177756e9890e143b0ad8d704201
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into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision : b73eeb1f73a5886a008919acd9e1971a79fd6bfb
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src/arch/mips/isa/formats/mt.isa:
change copyright to 2006
src/cpu/simple/base.cc:
Only DPRINT NNPC if we are not using ALPHA
src/cpu/static_inst.hh:
Take Out MIPS Specific functions ...
--HG--
extra : convert_revision : 7a69e80cd1564fa3b778b9dade0e9fe3cef94e64
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into vm1.(none):/home/stever/bk/newmem-py
src/python/m5/__init__.py:
src/sim/syscall_emul.cc:
Hand merge.
--HG--
extra : convert_revision : e2542735323e648383c89382421d98a7d1d761bf
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User script now invokes initialization and
simulation loop after building configuration.
These functions are exported from C++ to Python
using SWIG.
SConstruct:
Set up SWIG builder & scanner.
Set up symlinking of source files into build directory
(by not disabling the default behavior).
configs/test/test.py:
Rewrite to use new script-driven interface.
Include a sample option.
src/SConscript:
Set up symlinking of source files into build directory
(by not disabling the default behavior).
Add SWIG-generated main_wrap.cc to source list.
src/arch/SConscript:
Set up symlinking of source files into build directory
(by not disabling the default behavior).
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/trace/opt_cpu.cc:
src/cpu/trace/trace_cpu.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
src/sim/serialize.cc:
src/sim/syscall_emul.cc:
SimExit() is now exitSimLoop().
src/cpu/base.cc:
SimExitEvent is now SimLoopExitEvent
src/python/SConscript:
Add SWIG build command for main.i.
Use python/m5 in build dir as source for zip archive...
easy now with file duplication enabled.
src/python/m5/__init__.py:
- Move copyright notice back to C++ so we can print
it right away, even for interactive sessions.
- Get rid of argument parsing code; just provide default
option descriptors for user script to call optparse with.
- Don't clutter m5 namespace by sucking in all of m5.config
and m5.objects.
- Move instantiate() function here from config.py.
src/python/m5/config.py:
- Move instantiate() function to __init__.py.
- Param.Foo deferred type lookups must use m5.objects
namespace now (not m5).
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/AlphaFullCPU.py:
src/python/m5/objects/AlphaTLB.py:
src/python/m5/objects/BadDevice.py:
src/python/m5/objects/BaseCPU.py:
src/python/m5/objects/BaseCache.py:
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Bus.py:
src/python/m5/objects/CoherenceProtocol.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/IntrControl.py:
src/python/m5/objects/MemObject.py:
src/python/m5/objects/MemTest.py:
src/python/m5/objects/Pci.py:
src/python/m5/objects/PhysicalMemory.py:
src/python/m5/objects/Platform.py:
src/python/m5/objects/Process.py:
src/python/m5/objects/Repl.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/SimConsole.py:
src/python/m5/objects/SimpleDisk.py:
src/python/m5/objects/System.py:
src/python/m5/objects/Tsunami.py:
src/python/m5/objects/Uart.py:
Fix up imports (m5 namespace no longer includes m5.config).
src/sim/eventq.cc:
src/sim/eventq.hh:
Support for Python-called simulate() function:
- Use IsExitEvent flag to signal events that want
to exit the simulation loop gracefully (instead of
calling exit() to terminate the process).
- Modify interface to hand exit event object back to
caller so it can be inspected for cause.
src/sim/host.hh:
Add MaxTick constant.
src/sim/main.cc:
Move copyright notice back to C++ so we can print
it right away, even for interactive sessions.
Use PYTHONPATH environment var to set module path
(instead of clunky code injection method).
Move main control from here into Python:
- Separate initialization code and simulation loop
into separate functions callable from Python.
- Make Python interpreter invocation more pure (more
like directly invoking interpreter).
Add -i and -p flags (only options on binary itself;
other options processed by Python).
Import readline package when using interactive mode.
src/sim/sim_events.cc:
SimExitEvent is now SimLoopExitEvent, and uses
IsSimExit flag to terminate loop (instead of
exiting simulator process).
src/sim/sim_events.hh:
SimExitEvent is now SimLoopExitEvent, and uses
IsSimExit flag to terminate loop (instead of
exiting simulator process).
Get rid of a few unused constructors.
src/sim/sim_exit.hh:
SimExit() is now exitSimLoop().
Get rid of unused functions.
Add comments.
--HG--
extra : convert_revision : 280b0d671516b25545a6f24cefa64a68319ff3d4
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src/cpu/o3/lsq_unit_impl.hh:
Missed this name change.
src/cpu/thread_state.cc:
Fix for stats.
--HG--
extra : convert_revision : 50ea862f97f2fbc75c1c03d5700df1e8f2c0d122
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src/cpu/base_dyn_inst.cc:
Clean up old functions, comments.
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/ozone/lsq_unit.hh:
src/cpu/ozone/lsq_unit_impl.hh:
Remove old commented code.
src/cpu/o3/fetch.hh:
Remove old commented code, add in comments.
src/cpu/o3/inst_queue_impl.hh:
Move comment to better place.
src/cpu/o3/lsq_unit.hh:
Remove old commented code, add in new comments.
src/cpu/o3/lsq_unit_impl.hh:
Remove old commented code, rename variable.
--HG--
extra : convert_revision : 8e79af9b4d3b3bdd0f55e4747c6ab64c9ad2f571
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision : 184b6ff6c11de8f9c9083dcb93754cb451d9cfce
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--HG--
extra : convert_revision : ddbcf82e0a3160c93c4e51f5d60b0a7b5983d3ba
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--HG--
extra : convert_revision : 7b3324ed41e24b69b3e793005ebc07a7d72a3763
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src/cpu/o3/alpha_cpu.hh:
Remove functions no longer used for reading and writing.
--HG--
extra : convert_revision : aa2fde86ebad06a9a3a9628016b885ff546c0189
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retry. It should also be able to handle LL/SC (through hacks) for the UP case.
src/cpu/o3/lsq_unit.hh:
Handle being able to retry (untested but hopefully very close to working).
Handle lock flag for LL/SC hack. Hopefully the memory system will add in LL/SC soon.
Better output message.
src/cpu/o3/lsq_unit_impl.hh:
Handle being able to retry (untested but should be very close to working).
Make SC's work (hopefully) while the memory system doesn't have a LL/SC implementation.
--HG--
extra : convert_revision : bffa721b21405c88a9c6b3d9b9080957f8a2638f
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when we get a virtual port delete it (even though delete does nothing in these cases)
src/arch/alpha/linux/system.cc:
src/arch/alpha/stacktrace.cc:
src/base/remote_gdb.cc:
src/cpu/simple_thread.cc:
when we get a virtual port delete it (even though delete does nothing in this case)
src/mem/port.hh:
src/mem/vport.hh:
add write/read functions that have endian conversions in them
--HG--
extra : convert_revision : 163e05cc038c461f95c92f8ce55422033f9ea513
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to memory. As long as the checker does not access memory to verify the store's data (currently impossible in the O3 model), this will work fine.
src/cpu/o3/lsq_unit_impl.hh:
Tell checker that an instruction is completed prior once it does the access to memory.
--HG--
extra : convert_revision : 1d4bbac4b35fbd355f300eab76f29b38b5bc88cb
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--HG--
extra : convert_revision : 842556970ff6f0660e8bef13819a3ddfc048d8c8
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It still does not yet handle retries.
src/cpu/base_dyn_inst.hh:
Get working in full-system mode and fix some FP bugs.
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/thread_context.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/thread_state.hh:
Get working in full system.
src/cpu/checker/o3_cpu_builder.cc:
Checker does not take a MemObject as a simobj parameter.
src/cpu/o3/alpha_dyn_inst.hh:
Fix up float regs.
src/cpu/o3/regfile.hh:
Fix up an fp error, print out more useful output messages.
--HG--
extra : convert_revision : d7cc152a051c697f18b7ee9e14050fbf3ffa5966
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