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cpu
Age
Commit message (
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Author
2012-07-10
cpu: added assertions to ensure the correct proxies are used
Brad Beckmann
2012-07-09
Port: Align port names in C++ and Python
Andreas Hansson
2012-07-09
Port: Move retry from port base class to Master/SlavePort
Andreas Hansson
2012-07-09
Fix: Address a few benign memory leaks
Andreas Hansson
2012-06-29
O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.
Nathanael Premillieu
2012-06-08
Timing CPU: Remove a redundant port pointer
Andreas Hansson
2012-06-05
cpu: Don't init simple and inorder CPUs if they are defered.
Anthony Gutierrez
2012-06-05
ISA: Back-out NoopMachInst as a StaticInstPtr change.
Ali Saidi
2012-06-05
O3: Clean up the O3 structures and try to pack them a bit better.
Ali Saidi
2012-06-05
sim: Remove FastAlloc
Ali Saidi
2012-06-04
ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.
Gabe Black
2012-05-31
Bus: Split the bus into a non-coherent and coherent bus
Andreas Hansson
2012-05-30
Packet: Unify the use of PortID in packet and port
Andreas Hansson
2012-05-26
ISA,CPU: Generalize and split out the components of the decode cache.
Gabe Black
2012-05-26
CPU: Merge the predecoder and decoder.
Gabe Black
2012-05-25
ISA: Make the decode function part of the ISA's decoder.
Gabe Black
2012-05-25
CPU: Simplify the implementation of the decode cache.
Gabe Black
2012-05-25
Decode: Make the Decoder class defined per ISA.
Gabe Black
2012-05-10
gem5: fix some iterator use and erase bugs
Ali Saidi
2012-05-10
gem5: fix a number of use after free issues
Ali Saidi
2012-05-01
MEM: Separate requests and responses for timing accesses
Andreas Hansson
2012-04-25
MEM: Add the PortId type and a corresponding id field to Port
Andreas Hansson
2012-04-15
CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class.
Gabe Black
2012-04-14
Ruby: Use MasterPort base-class pointers where possible
Andreas Hansson
2012-04-14
MEM: Remove the Broadcast destination from the packet
Andreas Hansson
2012-04-14
MEM: Separate snoops and normal memory requests/responses
Andreas Hansson
2012-04-14
clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
Andreas Hansson
2012-04-06
rubytest: remove spurious printf
Brad Beckmann
2012-04-06
rubytest: seperated read and write ports.
Brad Beckmann
2012-04-06
MEM: Enable multiple distributed generalized memories
Andreas Hansson
2012-04-05
NetworkTest: remove unnecessary memory allocation
Tushar Krishna
2012-04-03
Atomic: Remove the physmem_port and access memory directly
Andreas Hansson
2012-03-30
MEM: Introduce the master/slave port sub-classes in C++
William Wang
2012-03-30
CPU: Unify initMemProxies across CPUs and simulation modes
Andreas Hansson
2012-03-22
Scons: Remove Werror=False in SConscript files
Andreas Hansson
2012-03-21
O3: Fix sizing of decode to rename skid buffer.
Andrew Lukefahr
2012-03-21
O3: Fix size of skid buffer between fetch and decode when widths are different
Brian Grayson
2012-03-19
gcc: Clean-up of non-C++0x compliant code, first steps
Andreas Hansson
2012-03-19
clang: Fix recently introduced clang compilation errors
Andreas Hansson
2012-03-11
O3: Add fatal when fetchWidth > Impl::MaxWidth.
Brian Grayson
2012-03-09
O3/Ozone: Eliminate dead code counting software prefetch insts
Geoffrey Blake
2012-03-09
CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
Geoffrey Blake
2012-03-09
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Geoffrey Blake
2012-03-02
DynInst: get rid of dead MyHash code.
Steve Reinhardt
2012-03-02
CPU: Check that the interrupt controller is created when needed
Andreas Hansson
2012-03-01
x86: Fix switching of CPUs
Nilay Vaish
2012-02-24
Ruby: Simplify tester ports by not using SimpleTimingPort
Andreas Hansson
2012-02-24
MEM: Move all read/write blob functions from Port to PortProxy
Andreas Hansson
2012-02-24
MEM: Make port proxies use references rather than pointers
Andreas Hansson
2012-02-24
MEM: Move port creation to the memory object(s) construction
Andreas Hansson
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