gem5 - gem5

Age	Commit message (Collapse)	Author
2009-03-04	Give each resource in InOrder it's own TraceFlag instead of just standard ↵	Korey Sewell
	'Resource' flag
2009-03-04	Remove unused functions/comments cluttering up the code.	Korey Sewell

2009-03-04	make handling of interstage buffers (i.e. StageQueues) more consistent: ↵	Korey Sewell
	(1)number from 0-n, not 1-n+1, (2) always check nextStageValid before a stageNum+1 and prevStageValid for a stageNum-1 reference (3) add skidSize() to get StageQueue size for all threads
2009-03-04	InOrder didnt have all it's params set to a default value, which is now ↵	Korey Sewell
	required for M5 objects; Also, a # of values need to be reset to 0 (or the appropriate value) before we assume they are OK for use.
2009-03-04	Give TimeBuffer an ID that can be set. Necessary because InOrder uses ↵	Korey Sewell
	generic stages so w/o an ID there is no way to differentiate buffers when debugging
2009-03-04	use numCycles instead of simTicks to determine CPI stat in InOrder	Korey Sewell

2009-03-04	O3: Make numThreads error message more helpful.	Steve Reinhardt

2009-02-27	Processes: Make getting and setting system call arguments part of a process ↵	Gabe Black
	object.
2009-02-26	CPA: Add code to automatically record function symbols as CPU executes.	Ali Saidi

2009-02-25	CPU: Only look up the nearest symbol in the kernel if you're actually in ↵	Gabe Black
	kernel code.
2009-02-25	CPU: Add a flag to identify a read barrier to the static inst class.	Gabe Black

2009-02-25	CPU: Don't fetch when executing a macroop.	Gabe Black
	If the CPL changes mid macroop, the end of the instruction might not be priveleged enough to execute the beginning.
2009-02-25	CPU: Implement translateTiming which defers to translateAtomic, and convert ↵	Gabe Black
	the timing simple CPU to use it.
2009-02-25	ISA: Replace the translate functions in the TLBs with translateAtomic.	Gabe Black

2009-02-25	CPU: Get rid of translate... functions from various interface classes.	Gabe Black

2009-02-23	debug: Move debug_break into src/base	Nathan Binkert

2009-02-20	Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up ↵	Korey Sewell
	comments and O3 extensions InOrder Thread Context
2009-02-16	Fixes to get prefetching working again.	Steve Reinhardt
	Apparently we broke it with the cache rewrite and never noticed. Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part of these changes (and for inspiring me to work on the rest). Some other overdue cleanup on the prefetch code too.
2009-02-10	style	Nathan Binkert

2009-02-10	Configs: Add support for the InOrder CPU model	Korey Sewell

2009-02-10	InOrder: Import new inorder CPU model from MIPS.	Korey Sewell
	This model currently only works in MIPS_SE mode, so it will take some effort to clean it up and make it generally useful. Hopefully people are willing to help make that happen!
2009-02-10	ExeTrace: Allow subclasses of the tracer to define their own prefix to dump	Korey Sewell

2009-02-10	CPU: Prepare CPU models for the new in-order CPU model.	Korey Sewell
	Some new functions and forward declarations are necessary to make things work
2009-02-01	CPU: Don't always reset the micro pc on faults. Let the faults handle it.	Gabe Black

2009-02-01	X86: Make sure the predecoder is cleared out for interrupts.	Gabe Black

2009-01-30	Config: Cause a fatal() when a parameter without a default value isn't ↵	Ali Saidi
	set(FS #315).
2009-01-25	CPU: Add a setCPU function to the interrupt objects.	Gabe Black

2009-01-24	cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep.	Nathan Binkert
	Make interrupts use the new wakeup method, and pull all of the interrupt stuff into the cpu base class so that only the wakeup code needs to be updated. I tried to make wakeup, wakeCPU, and the various other mechanisms for waking and sleeping a little more sane, but I couldn't understand why the statistics were changing the way they were. Maybe we'll try again some day.
2009-01-21	o3cpu: give a name to the activity recorder for better tracing	Nathan Binkert

2009-01-19	thread_context: move getSystemPtr so SE mode can get to it.	Nathan Binkert
	There was really no reason that it should be FS only.
2009-01-13	SCons: centralize the Dir() workaround for newer versions of scons.	Nathan Binkert
	Scons bug id: 2006 M5 Bug id: 308
2009-01-11	This fix addresses an ill formed if statement that fails	Richard Strong
	to compile. The fix was the simple addition of another set of parenthesis to ensure the correct condition resolution.
2009-01-06	Tracing: Make tracing aware of macro and micro ops.	Gabe Black

2008-12-17	Make Alpha pseudo-insts available from SE mode.	Steve Reinhardt

2008-12-16	SPARC: Truncate syscall args and return values appropriately.	Gabe Black

2008-12-06	eventq: use the flags data structure	Nathan Binkert

2008-11-13	CPU: Refactor read/write in the simple timing CPU.	Gabe Black

2008-11-10	O3CPU: Make the instcount debugging stuff per-cpu.	Clint Smullen
	This is to prevent the assertion from firing if you have a large multicore. Also make sure that it's not compiled in when NDEBUG is defined
2008-11-10	mem: update stuff for changes to Packet and Request	Nathan Binkert

2008-11-09	CPU: Make unaligned accesses work in the timing simple CPU.	Gabe Black

2008-11-09	X86: Make the timing simple CPU handle variable length instructions.	Gabe Black

2008-11-05	Right now a single thread cpu 1 could get assigned context Id != 1, depending	Lisa Hsu
	on the order in which it's registered with the system. To make them match, here is a little change.
2008-11-04	get rid of all instances of readTid() and getThreadNum(). Unify and eliminate	Lisa Hsu
	redundancies with threadId() as their replacement.
2008-11-02	Add in Context IDs to the simulator. From now on, cpuId is almost never used,	Lisa Hsu
	the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate.
2008-11-02	Make it so that all thread contexts are registered with the System, even in	Lisa Hsu
	SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration.
2008-11-02	make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered	Lisa Hsu
	across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch.
2008-10-27	CPU: The API change to EventWrapper did not get propagated to the entirety ↵	Clint Smullen
	of TimingSimpleCPU. The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning. Signed-off By: Ali Saidi
2008-10-23	s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in	Lisa Hsu
	comments.
2008-10-21	style: Use the correct m5 style for things relating to interrupts.	Nathan Binkert

2008-10-20	O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. ↵	Ali Saidi
	Removing hwrei causes the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal call sys and thus the translation fails because the user is attempting to access a super page address. Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs. Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were removed since a great deal of manual patching would be required to only remove the hwrei change.