gem5 - gem5

Age	Commit message (Expand)	Author
2012-02-24	MEM: Make port proxies use references rather than pointers	Andreas Hansson
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
2012-02-24	CPU: Round-two unifying instr/data CPU ports across models	Andreas Hansson
2012-02-13	BPred: Fix RAS to handle predicated call/return instructions.	Mrinmoy Ghosh
2012-02-13	BP: Fix several Branch Predictor issues.	Mrinmoy Ghosh
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	cpu: add separate stats for insts/ops both globally and per cpu model	Anthony Gutierrez
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-02-10	O3 CPU: Improve handling of delayed commit flag	Nilay Vaish
2012-02-10	O3 CPU: Strengthen condition for handling interrupts	Nilay Vaish
2012-02-10	O3 CPU: Provide the squashing instruction	Nilay Vaish
2012-02-10	O3 Fetch: Check if PC is pointing to Microcode ROM	Nilay Vaish
2012-02-10	SE/FS: Record the system pointer all the time for the simple CPU.	Gabe Black
2012-02-07	Checker: Access workload element 0 only if there is an element 0.	Gabe Black
2012-02-07	Faults: Turn off arch/faults.hh	Gabe Black
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-31	Thread: Use inherited baseCpu rather than cpu in SimpleThread	Andreas Hansson
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-30	Merge with main repository.	Gabe Black
2012-01-30	MEM: Clean-up of Functional/Virtual/TranslatingPort remnants	Andreas Hansson
2012-01-29	Yet another merge with the main repository.	Gabe Black
2012-01-29	Implement Ali's review feedback.	Gabe Black
2012-01-28	O3 CPU LSQ: Implement TSO	Nilay Vaish
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-16	Merge yet again with the main repository.	Gabe Black
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	MEM: Simplify ports by removing EventManager	Andreas Hansson
2012-01-17	CPU: Moving towards a more general port across CPU models	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2012-01-12	inorder: MDU deadlock fix	Maximilien Breughe
2012-01-10	DPRINTF: Improve some dprintf messages.	Nilay Vaish
2012-01-09	CPU: Remove Alpha-specific PC alignment check.	Anders Handler
2012-01-09	O3: Remove some asserts that no longer seem to be valid.	Ali Saidi
2012-01-09	O3: Add support of function tracing with O3 CPU.	Ali Saidi
2012-01-09	MAC: Make gem5 compile and run on MacOSX 10.7.2	Andreas Hansson
2012-01-07	Another merge with the main repository.	Gabe Black
2012-01-07	Merge with the main repository again.	Gabe Black
2012-01-07	Merge with main repository.	Gabe Black
2011-12-13	gcc: fix unused variable warnings from GCC 4.6.1	Nathan Binkert
2011-12-01	Output: Add hierarchical output support and cleanup existing codebase.	Chris Emmons
2011-12-01	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	Chander Sudanthi
2011-12-01	ARM: Add support for having a TLB cache.	Ali Saidi
2011-12-01	O3: Add stat that counts how many cycles the O3 cpu was quiesced.	Ali Saidi
2011-11-18	SE/FS: Get rid of includes of config/full_system.hh.	Gabe Black
2011-11-18	SE/FS: Get rid of FULL_SYSTEM in the CPU directory.	Gabe Black
2011-11-03	Ruby: Remove some unused typedefs	Nilay Vaish
2011-11-02	SE/FS: Get rid of FULL_SYSTEM in sim.	Gabe Black
2011-11-01	SE/FS: Get rid of uses of FULL_SYSTEM in Alpha.	Gabe Black
2011-11-01	SE/FS: Expose the same methods on the CPUs in SE and FS modes.	Gabe Black