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path: root/src/cpu
AgeCommit message (Expand)Author
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20cpu: Update DRAM traffic genWendy Elsasser
2014-09-20base: Clean up redundant string functions and use C++11Andreas Hansson
2014-09-20cpu: Add ExecFlags debug flagMitch Hayenga
2014-09-20cpu: use probes infrastructure to do simpoint profilingDam Sunwoo
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-09-19cpu: Use a deque in o3 rename instruction queueAndreas Hansson
2014-09-19misc: Use safe_cast when assumptions are made about return valueAndreas Hansson
2014-09-12cpu: Fix memory access in Minor not setting parent Request flagsAndrew Bardsley
2014-09-12style: Fix line continuation, especially in debug messagesAndrew Bardsley
2014-09-12minor: Fix typo in DPRINTF for Minor branch predictionAndreas Hansson
2014-09-09cpu: Only iterate over possible threads on the o3 cpuMitch Hayenga
2014-09-09misc: Fix a number of unitialised variables and membersAndreas Hansson
2014-09-03base: Use the global Mersenne twister throughoutAndreas Hansson
2014-05-13mem: Refactor assignment of Packet typesCurtis Dunham
2014-09-03cpu: Fix o3 drain bugMitch Hayenga
2014-04-29arm: use condition code registers for ARM ISACurtis Dunham
2014-09-03cpu: fix bimodal predictor to use correct global history regDam Sunwoo
2014-09-03cpu: Fix cache blocked load behavior in o3 cpuMitch Hayenga
2014-09-03cpu: Fix o3 quiesce fetch bugMitch Hayenga
2014-09-03cpu: Fix SMT scheduling issue with the O3 cpuMitch Hayenga
2014-09-03cpu: Fix incorrect speculative branch predictor behaviorMitch Hayenga
2014-09-03cpu: Add a fetch queue to the o3 cpuMitch Hayenga
2014-09-03cpu: Fix o3 front-end pipeline interlock behaviorMitch Hayenga
2014-09-03cpu: Change writeback modeling for outstanding instructionsMitch Hayenga
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-09-01mem: change the namespace Message to ProtoMessageNilay Vaish
2014-09-01ruby: eliminate type TimeNilay Vaish
2014-08-13scons: Build the branch predictor for all CPUsAndreas Sandberg
2014-08-13cpu: Don't forward declare RefCountingPtrAndreas Sandberg
2014-08-13cpu: Modernise the branch predictor (STL and C++11)Andreas Hansson
2014-08-10cpu: Ensure the traffic generator suppresses non-memory packetsAndreas Hansson
2014-07-23cpu: `Minor' in-order CPU modelAndrew Bardsley
2014-06-30cpu: implement a bi-mode branch predictorAnthony Gutierrez
2014-06-21o3: make dispatch LSQ full check more selectiveBinh Pham
2014-06-21o3: split load & store queue full cases in renameBinh Pham
2014-05-31style: eliminate equality tests with true and falseSteve Reinhardt
2014-05-23cpu: o3: remove stat totalCommittedInstsNilay Vaish
2014-05-09cpu: Useful getters for ActivityRecorderAndrew Bardsley
2014-05-09cpu: Add flag name printing to StaticInstAndrew Bardsley
2014-05-09cpu: Timebuf const accessorsAndrew Bardsley
2014-05-09arch, arm: Preserve TLB bootUncacheability when switching CPUsGeoffrey Blake
2014-05-09cpu: add more instruction mix statisticsCurtis Dunham
2014-05-09cpu, arm: Allow the specification of a socket fieldAkash Bagdia
2014-04-23cpu: Fix setTranslateLatency() bug for squashed instructionsMitchell Hayenga
2014-04-01cpu: Fix case where o3 lsq could print out uninitialized dataMitch Hayenga
2014-04-23cpu: Add O3 CPU width checksDam Sunwoo
2014-04-19o3: Fix occupancy checks for SMTFaissal Sleiman
2014-04-09kvm, x86: Add initial support for multicore simulationAndreas Sandberg