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path: root/src/cpu
AgeCommit message (Expand)Author
2019-03-14cpu: Refactor of Physical Register implementationAndrea Mondelli
2019-03-14arch-arm,cpu: Add initial support for Arm SVEGiacomo Gabrielli
2019-03-01mem-cache: alias to mem::getMasterPort in TLB classAndrea Mondelli
2019-02-27misc: Segmentation Fault during O3PipeView executionAndrea Mondelli
2019-02-26cpu: Fix indirect branch history updatesSrikant Bharadwaj
2019-02-22python: Fix param -> int conversion issuesAndreas Sandberg
2019-02-22cpu-o3: Add cache read ports limit to LSQGabor Dozsa
2019-02-22python: Make iterator handling Python 3 compatibleAndreas Sandberg
2019-02-19cpu: Add ISA* getter in Thread interfaceGiacomo Gabrielli
2019-02-15cpu: Fix fast build broken due to unused variableGiacomo Travaglini
2019-02-13cpu: Added 8KB and 64KB TAGE-SC-L branch predictorJavier Bueno
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2019-02-08cpu: Proposal for changing the indirect branch predictor interfaceJairo Balart
2019-02-08cpu: support atomic memory request type with AtomicOpFunctorTuan Ta
2019-02-08cpu: fix how branching is handled when a thread is suspended in MinorCPUTuan Ta
2019-02-08cpu: stop scheduling suspended threads in all stages of MinorCPUTuan Ta
2019-02-08sim,cpu: make exit_group halt all threads in a groupTuan Ta
2019-02-08cpu: fixed how O3 CPU executes an exit system callTuan Ta
2019-02-06cpu: fix how a thread starts up in MinorCPUTuan Ta
2019-02-05misc: added missing override specifierAndrea Mondelli
2019-02-05cpu: Made the Loop Predictor a SimObjectJavier Bueno
2019-02-05cpu: Made TAGE a SimObject that can be used by other predictorsJairo Balart
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-25cpu, arch, arch-arm: Wire unused VecElem code in the O3 modelGiacomo Travaglini
2019-01-25cpu: O3 rename using the flatIndex instead of indexGiacomo Travaglini
2019-01-25cpu: Fix VecElemClass bugs in cpu modelsGiacomo Travaglini
2019-01-25cpu: Add VecElem entries in MinorCPU ScoreboardGiacomo Travaglini
2019-01-24cpu-o3: O3 LSQ GeneralisationRekai Gonzalez-Alberquilla
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
2019-01-17cpu-o3: Make the smtCommitPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtROBPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtIQPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtLSQPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtFetchPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2019-01-15cpu: Fix usage of setArchVecElemGiacomo Travaglini
2018-12-22cpu: Stop using unions to store FP registers.Gabe Black
2018-12-20arch, cpu: Remove float type accessors.Gabe Black
2018-12-11cpu: Fixed typos in parameter/stats descriptionsPau Cabre
2018-12-11cpu: Added parameters to enable/disable features in LTAGEPau Cabre
2018-12-11cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctorTony Gutierrez
2018-12-04base, sim: Add missing destructorsNikos Nikoleris
2018-12-03cpu: Change raw pointers to STL ContainersRekai Gonzalez-Alberquilla
2018-11-28cpu: Added new stats to TAGE and LTAGE branch predictorsPau Cabre
2018-11-28cpu: split LTAGE implementation into a base TAGE and a derived LTAGEPau Cabre
2018-11-28cpu,arch-arm: Initialise data membersRekai Gonzalez-Alberquilla
2018-11-27arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.Gabe Black
2018-11-22cpu: Made LTAGE parameters configurablePau Cabre
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