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AgeCommit message (Expand)Author
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2019-01-15cpu: Fix usage of setArchVecElemGiacomo Travaglini
2018-12-22cpu: Stop using unions to store FP registers.Gabe Black
2018-12-20arch, cpu: Remove float type accessors.Gabe Black
2018-12-11cpu: Fixed typos in parameter/stats descriptionsPau Cabre
2018-12-11cpu: Added parameters to enable/disable features in LTAGEPau Cabre
2018-12-11cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctorTony Gutierrez
2018-12-04base, sim: Add missing destructorsNikos Nikoleris
2018-12-03cpu: Change raw pointers to STL ContainersRekai Gonzalez-Alberquilla
2018-11-28cpu: Added new stats to TAGE and LTAGE branch predictorsPau Cabre
2018-11-28cpu: split LTAGE implementation into a base TAGE and a derived LTAGEPau Cabre
2018-11-28cpu,arch-arm: Initialise data membersRekai Gonzalez-Alberquilla
2018-11-27arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.Gabe Black
2018-11-22cpu: Made LTAGE parameters configurablePau Cabre
2018-11-22cpu: Fixed useful counter handling in LTAGEPau Cabre
2018-11-22cpu: Fixes on the loop predictor part of LTAGEPau Cabre
2018-11-17cpu: Fix LTAGE max number of allocations on updatePau Cabre
2018-11-17configs: Added an option for choosing branch predictor typePau Cabre
2018-11-16cpu: Fix the usage of const DynInstPtrRekai Gonzalez-Alberquilla
2018-11-14cpu: Fixed ratio of pred to hyst bits for LTAGE BimodalPau Cabre
2018-11-13cpu: Fixed PC shifting on LTAGE branch predictorPau Cabre
2018-10-09cpu: Fix MinorCPU executing Crypto InstructionsGiacomo Travaglini
2018-10-09arch-arm: AArch32 Crypto AESMatt Horsnell
2018-10-09arch-arm: AArch32 Crypto SHAMatt Horsnell
2018-10-01cpu: Fix typo in header guard for Noncaching cpuGiacomo Travaglini
2018-09-13Fix SConstruct for asan buildEarl Ou
2018-09-12cpu: Replace the fastmem with a new CPU modelAndreas Sandberg
2018-08-24cpu: Stream/SubstreamID support in TrafficGenGiacomo Travaglini
2018-08-24cpu: Turn BaseTrafficGen numSuppressed into a statMichiel W. van Tol
2018-08-21misc: Appease GCC 8Jason Lowe-Power
2018-08-17scons,ruby: do not generate unnecessary filesBrandon Potter
2018-08-10cpu: Add hash functionality for RegId classBradley Wang
2018-08-10cpu: Removed unnecessary file reg_class_impl.hhBradley Wang
2018-07-25cpu: Warn when (un)serializing a traffic generatorGiacomo Travaglini
2018-07-25cpu: Allow creation of traffic gen from generic SimObjectsGiacomo Travaglini
2018-07-24cpu-o3: Missing freeing the heads of DepGraph in IQ squashingHanhwi Jang
2018-07-13cpu: Add a Python-enabled traffic generatorAndreas Sandberg
2018-07-13cpu: Support trace termination in BaseTrafficGenAndreas Sandberg
2018-07-13cpu: Unify error handling for address generatorsAndreas Sandberg
2018-07-13cpu: Split the traffic generator into two classesAndreas Sandberg
2018-06-28cpu: Remove reduntant protobuf includesAndreas Sandberg
2018-06-21cpu: Fix bug introduced by RequestPtr type changeGiacomo Travaglini
2018-06-14cpu: Prevent suspended TimingSimple CPUs from fetching next instructionsTuan Ta
2018-06-14cpu: add a new instruction type 'Atomic'Tuan Ta
2018-06-14cpu-minor: Remove redundant thread startup callAndreas Sandberg
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
2018-05-29cpu: Avoid unnecessary dynamic_pointer_cast in atomic modelGiacomo Travaglini
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
2018-03-27cpu: Remove ExtMachInst typedefs from the O3 CPU model.Gabe Black
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