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path: root/src/cpu
AgeCommit message (Expand)Author
2019-08-07cpu-o3: fix atomic instructions non-speculativeJordi Vaquero
2019-08-07cpu-o3: added _amo_op parameter in o3 LSQJordi Vaquero
2019-07-28cpu: Fix the type of the effective mem request sizeGabor Dozsa
2019-07-28cpu-o3: Fix too strict assert condition in writeback()Gabor Dozsa
2019-07-27cpu: Add first-/non-faulting load support to Minor and O3Gabor Dozsa
2019-07-16cpu: isDrained renamed to isCpuDrainedGiacomo Travaglini
2019-07-13cpu-o3: Set packet data type for IPR readPouya Fotouhi
2019-07-08cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)Javier Bueno Hedo
2019-07-08cpu-o3: Reset fault status for mem access in pushRequestGabor Dozsa
2019-06-11cpu: Additional TrafficGen statsTiago Muck
2019-06-11cpu: Limit TrafficGen outstanding reqsTiago Muck
2019-06-11cpu: TrafficGen as BaseCPUTiago Muck
2019-06-03cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)Javier Bueno
2019-05-31cpu-o3: Increase LSQ buffer sizes to match max vector lengthGabor Dozsa
2019-05-30cpu: Fix rescheduling of progress check eventsTiago Muck
2019-05-30cpu-o3: Add support for pinned writesGiacomo Gabrielli
2019-05-30arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.Gabe Black
2019-05-30cpu: Store the translating proxy with the same pointer in SE or FS mode.Gabe Black
2019-05-30cpu, sim: Return PortProxy &s from all the proxy accessors.Gabe Black
2019-05-29cpu: Added correct return type for ROB::countInstsAndrea Mondelli
2019-05-28cpu: Remove assert causing issues with x86 Linux bootGiacomo Gabrielli
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
2019-05-14Revert "cpu: fix how a thread starts up in MinorCPU"Giacomo Travaglini
2019-05-14Revert "cpu: stop scheduling suspended threads in MinorCPU"Giacomo Travaglini
2019-05-14Revert "cpu: fix branching when thread is suspended in MinorCPU"Giacomo Travaglini
2019-05-14base: Move SatCounter to base directoryDaniel
2019-05-14cpu: Revamp saturating countersDaniel
2019-05-13cpu: Make the indirect predictor into a SimObjectJairo Balart
2019-05-11cpu,mem: Add support for partial loads/stores and wide mem. accessesGiacomo Gabrielli
2019-05-11cpu: Add a memory access predicateGiacomo Gabrielli
2019-04-30cpu: alpha: Delete all occurrances of the simPalCheck function.Gabe Black
2019-04-30cpu: Remove hwrei from the generic interfaces.Gabe Black
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
2019-04-29cpu: Get rid of the (read|set)RegOtherThread methods.Gabe Black
2019-04-29cpu: Include debug flags regardless of whether the ISA is null.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-24cpu,mem: missing override specifierAndrea Mondelli
2019-04-22cpu: Eliminate the ProxyThreadContext class.Gabe Black
2019-04-10cpu: O3 switchFreeList checking VecElems instead of FloatRegsGiacomo Travaglini
2019-04-05cpu: Correctly account for executed instructions in simple cpusNikos Nikoleris
2019-04-03misc: Removed inconsistency in O3* debug msgsAndrea Mondelli
2019-04-03arch-mips: added missing override specifier (o3)Andrea Mondelli
2019-03-28cpu: Added a probe to notify the address of retired instructionsJavier Bueno
2019-03-27cpu: Fixed the indirect branch predictor GHR handlingPau Cabre
2019-03-23misc: missing override specifierAndrea Mondelli
2019-03-21cpu-kvm: Added informative error messageRyan Gambord
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-14cpu: Refactor of Physical Register implementationAndrea Mondelli
2019-03-14arch-arm,cpu: Add initial support for Arm SVEGiacomo Gabrielli
2019-03-01mem-cache: alias to mem::getMasterPort in TLB classAndrea Mondelli
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