gem5 - gem5

Age	Commit message (Expand)	Author
2019-09-13	dev: Enable DTB IOMMU binding with a DMA object	Giacomo Travaglini
2019-05-03	dev: StreamID generation in DMA device	Giacomo Travaglini
2019-04-28	mem: Minimize the use of MemObject.	Gabe Black
2019-02-12	python: Don't assume SimObjects live in the global namespace	Andreas Sandberg
2018-01-29	arm: DT autogeneration - autogenerate RealView Platform devices	Glenn Bergmans
2016-12-19	python: Fix incorrect header in the DmaDevice wrapper	Andreas Sandberg
2014-03-23	dev: Fix IsaFake's cxx_header setting	Andrew Bardsley
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-09-10	Device: Bump PIO and PCI latencies to more reasonable values	Andreas Hansson
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-08-21	Device: Remove overloaded pio_latency parameter	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-17	MEM: Removing the default port peer from Python ports	Andreas Hansson
2011-10-04	SE/FS: Put platform pointers in fewer objects.	Gabe Black
2011-07-10	IO: Handle case where ISA Fake device is being used as a fake memory.	Ali Saidi
2008-07-16	mem: use single BadAddr responder per system.	Steve Reinhardt
2007-05-27	Move SimObject python files alongside the C++ and fix	Nathan Binkert