gem5 - gem5

Age	Commit message (Collapse)	Author
2016-09-22	arm: disable GIC extensions	Curtis Dunham
	Change-Id: If19b9c593b48ded1ea848f2d3710d4369ec8a221 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26	dev, arm: Add a flag to enable/disable gem5 GIC extensions	Andreas Sandberg
	Make it possible to disable gem5 gic extensions by setting the gem5_extensions param to False from Python. Change-Id: Icb255105925ef49891d69cc9fe5cc55578ca066d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Geoffrey Blake <geoffrey.blake@arm.com>
2015-03-19	arm: Add a GICv2m device	Matt Evans
	This patch adds a new PIO-accessible GICv2m shim. This shim has a PIO slave port on one side, and SPI 'wires' on the other. It accepts MSIs from the system and triggers SPIs on the GIC. It is configurable with a number of frames, each of which has a number of SPIs and a base SPI offset. A Linux driver for GICv2m is available upstream.
2015-03-19	arm: Remove the 'magic MSI register' in the GIC (PL390)	Matt Evans
	This patch removes the code that added this magic register. A follow-up patch provides a GICv2m MSI shim that gives the same functionality in a standard ARM system architecture way.
2013-10-31	dev: Add support for MSI-X and Capability Lists for ARM and PCI devices	Geoffrey Blake
	This patch adds the registers and fields to the PCI device to support Capability lists and to support MSI-X in the GIC.
2012-10-25	arm: Create a GIC base class and make the PL390 derive from it	Andreas Sandberg
	This patch moves the GIC interface to a separate base class and makes all interrupt devices use that base class instead of a pointer to the PL390 implementation. This allows us to have multiple GIC implementations. Future implementations will allow in-kernel GIC implementations when using hardware virtualization. --HG-- rename : src/dev/arm/gic.cc => src/dev/arm/gic_pl390.cc rename : src/dev/arm/gic.hh => src/dev/arm/gic_pl390.hh