gem5 - gem5

Age	Commit message (Expand)	Author
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2016-08-02	arm: s/ctx_id/ctx/ the GIC	Curtis Dunham
2016-08-02	arm: bank GIC registers per CPU	Curtis Dunham
2016-05-26	dev, arm: Add a flag to enable/disable gem5 GIC extensions	Andreas Sandberg
2016-05-06	dev, arm: Update GIC to use GICv2 register naming	Andreas Sandberg
2015-09-18	dev, arm: Add gem5 extensions to support more than 8 cores	Karthik Sangaiah
2015-11-11	dev, arm: Initialized the iccrpr register in the GIC	Andreas Sandberg
2015-08-07	base: Declare a type for context IDs	Andreas Sandberg
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-04-29	arch, base, dev, kern, sym: FreeBSD support	Ruslan Bukin
2015-03-19	arm: Remove the 'magic MSI register' in the GIC (PL390)	Matt Evans
2015-02-16	arm: Wire up the GIC with the platform in the base class	Andreas Sandberg
2014-12-02	mem: Remove redundant Packet::allocate calls	Andreas Hansson
2014-09-03	dev: Avoid invalid sized reads in PL390 with DPRINTF enabled	Mitch Hayenga
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2013-10-31	dev: Add support for MSI-X and Capability Lists for ARM and PCI devices	Geoffrey Blake
2013-10-17	arm: Add a 'clear PPI' method to gic_pl390	Matt Evans
2013-10-17	arm: Fix a GIC mask register bug	Ali Saidi
2013-02-19	scons: Fix up numerous warnings about name shadowing	Andreas Hansson
2012-10-25	arm: Create a GIC base class and make the PL390 derive from it	Andreas Sandberg