gem5 - gem5

Age	Commit message (Expand)	Author
2016-08-02	arm: s/ctx_id/ctx/ the GIC	Curtis Dunham
2016-08-02	arm: bank GIC registers per CPU	Curtis Dunham
2016-05-26	dev, arm: Add a flag to enable/disable gem5 GIC extensions	Andreas Sandberg
2016-05-06	dev, arm: Update GIC to use GICv2 register naming	Andreas Sandberg
2015-09-18	dev, arm: Add gem5 extensions to support more than 8 cores	Karthik Sangaiah
2015-10-23	arm: Add missing explicit overrides for ARM devices	Andreas Hansson
2015-10-12	misc: Remove redundant compiler-specific defines	Andreas Hansson
2015-08-07	base: Declare a type for context IDs	Andreas Sandberg
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-03-19	arm: Remove the 'magic MSI register' in the GIC (PL390)	Matt Evans
2013-10-31	dev: Add support for MSI-X and Capability Lists for ARM and PCI devices	Geoffrey Blake
2013-10-17	arm: Add a 'clear PPI' method to gic_pl390	Matt Evans
2012-10-25	arm: Don't export private GIC methods	Andreas Sandberg
2012-10-25	arm: Create a GIC base class and make the PL390 derive from it	Andreas Sandberg