| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-10-01 | dev-arm: Enable FIQ signaling for Group0 interrupts in GICv2 | Giacomo Travaglini |
| 2018-10-01 | dev-arm: Create postFiq events for GICv2 | Giacomo Travaglini |
| 2018-10-01 | dev-arm: Implement GICv2 GICD_IGROUPR register | Giacomo Travaglini |
| 2018-10-01 | dev-arm: Fix GICv2 cpu interrupt enable flag | Giacomo Travaglini |
| 2018-10-01 | dev-arm: Add basic support for level sensitive SPIs in GICv2 | Adrien Pesle |
| 2018-09-28 | dev-arm: Take into account PPI enable bit | Giacomo Travaglini |
| 2018-09-12 | dev-arm: rename Pl390 to GicV2 | Ciro Santilli |
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index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |