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2019-09-09dev-arm: Fix GICv3 ITS cmdq wrappingGiacomo Travaglini
Change-Id: I979e8d1378d5b5d2647158798479cf4238f2c349 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20633 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-06dev-arm: Allow 32-bit access to GITS_TYPERGiacomo Travaglini
Change-Id: I9d19174b38ba70f82050102f955ccc162965d1fb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20618 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Rewrite GICv3 updateGiacomo Travaglini
The GICv3 update methods are method which are invoked anytime the model needs to evaluate a change in its state, which most of the time means managing the state of an interrupt (forwarding it to a PE, deasserting it, etc). The way it is currently done is a little bit obscure and doesn't handle correctly IRQ prioritization. Example: An IRQ which is handled by the redistributor (PPI or LPI) was not competing with any pending interrupts coming from the distributor (SPIs) once raised by a peripheral. Also the way the pending state of an interrupt was removed at the cpu interface level wasn't happening in place where this was actually happening (E.g. when activating it), but happened with a weird fullUpdate semantic, where if there was a pending interrupt in a cpu interface, all cpu interfaces had their pending interrupt (if any) been disabled. With this patch, state update always starts at the distributor, and it goes down until the cpu interface where a Gicv3CPUInterface::update method selects the winning interrupt coming from distributor/redistributor to be forwarded to the PE. Change-Id: I1c517cbc4bf107cc2d7ae7beb2692e3cf5187a40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20614 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-26dev-arm: Fix GICv3 ITS indexing errorGiacomo Travaglini
Table walks were not considering the entry size when evaluating the address. Change-Id: Ica6bf6d88632985ee8ed120448b32e0f7e918a8a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20329 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-26dev-arm: Fix GITS_BASER initialization/accessGiacomo Travaglini
The patch is fixing/improving GITS_BASER registers initialization. * Not using reserved table types anymore (GITS_BASER.TYPE) * Using write mask for handling WI bits Change-Id: Ibe24667fdf22b42b86496167c19fc00bbb0ba191 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20328 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-22dev-arm: Start using GITS_CTLR.quiescent bitGiacomo Travaglini
The GITS_CTLR.quiescent bit is used by priviledged sw to check when the ITS has finished draining its state (all pending translations/table walks have ended) once it has been disabled (by setting the GITS_CTLR.enable bit to 0). This patch is modelling this behaviour by * Changing the reset state to enable=0, quiescent=1 * Making the GITS_CTLR.quiescent bit RO * Updating the bit once a new translation/command is being processed (quiescent=0) and when there are no pending translation/commands (quiescent=1) Change-Id: I7cfe94b25d603400364b1cdfc2d2397acf5dfad8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20257 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-22dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR/BASER)Giacomo Travaglini
For those registers (GITS_CWRITER, GITS_READR and GITS_CBASER) Bits [63:32] and bits [31:0] are accessible separately. Change-Id: Ibf60b5e4fd20efb21a63570e6012862e37946877 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20256 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20dev-arm: Add GITS_PIDR2 register to the ITS memory mapGiacomo Travaglini
The GITS Peripheral Identification Register #2 bits assignments are the same as those for GICD_PIDR2. Change-Id: I235008a383e08dd557d899cb3aa18202ef943f8b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20254 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-22dev-arm: Provide a GICv3 ITS ImplementationGiacomo Travaglini
This patch introduces the GICv3 ITS module, which is in charge of translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The patch is only GICv3 compliant, which means that there is no direct virtual LPI injection (this also means V* commands are unimplemented) Other missing features are: * No 2level ITS tables (only flat table supported) * Command errors: when there is an error in the ITS, it is IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible scenarios (see GICv3 TRM) and this implementation only supports one of these (which is, aborting the command and jumping to the next one). Furter patches could make it possible to select different reactions * Invalidation commands (INV, INVALL) are only doing the memory table walks, assuming the current Gicv3Redistributor is not caching any configuration table entry. Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>