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AgeCommit message (Expand)Author
2019-05-02dev-arm: Store a PhysProxy port in Gicv3RedistGiacomo Travaglini
2019-05-02dev-arm: Add named variable for GICD_TYPER.IDBitsGiacomo Travaglini
2019-05-02dev-arm: Read correct version of ICC_BPR registerGiacomo Travaglini
2019-05-02dev-arm: Get a Gicv3Redistributor ptr from phys addressGiacomo Travaglini
2019-05-02dev-arm: Add several LPI methods in Gicv3RedistributorGiacomo Travaglini
2019-05-02dev-arm: Take LPIs into account when interacting with CPUIF regsGiacomo Travaglini
2019-05-02dev-arm: Fix GICv3 LPIs priority valueGiacomo Travaglini
2019-05-02dev-arm: Disable LPI Configuration Table cachingGiacomo Travaglini
2019-05-02dev-arm: Check EnableLPIs before checking for pending LPIsGiacomo Travaglini
2019-05-02dev-arm: GICv3 LPI tables are using physical addressesGiacomo Travaglini
2019-05-02dev-arm: Fix GICv3 LPI loopGiacomo Travaglini
2019-05-02dev-arm: Fix Bitwise operation in GICv3Giacomo Travaglini
2019-04-25dev-arm: Move GICv3 (Re)Ditributor address in Realview.pyGiacomo Travaglini
2019-04-25dev-arm: Limit number of max PE in GICv3 to 128Giacomo Travaglini
2019-04-25dev-arm: Add GICv4 extension switch in GICv3Giacomo Travaglini
2019-04-25dev-arm: Check for maximum number of supported PE in GICv3Giacomo Travaglini
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
2019-03-27dev-arm: Rename GIC maintenance interrupt from ppint to maint_intGiacomo Travaglini
2019-03-27dev-arm: Fix GICv3 overflow for INTID > 256Giacomo Travaglini
2019-03-27dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)Giacomo Travaglini
2019-03-26dev-arm: Set/Unset dma coherent mode from pythonGiacomo Travaglini
2019-03-14dev-arm: cleanup of gicv3 CPU interface code and fixesJairo Balart
2019-03-12dev-arm: cleanup of gicv3 codeJairo Balart
2019-03-01dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on readsGiacomo Travaglini
2019-03-01dev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping on readsGiacomo Travaglini
2019-02-18dev-arm: LPI support for GICv3. This doesn't include an ITS model.Jairo Balart
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2019-02-07configs, arch-arm: Using AddrRange for Realview mem_regionsGiacomo Travaglini
2019-02-01dev, arm: Removed contextId variableAnouk Van Laer
2019-01-24dev-arm: fix --generate-dtb for ARMCiro Santilli
2019-01-22arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.Gabe Black
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2019-01-10dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 supportJairo Balart
2019-01-10dev-arm: Add a GICv3 modelJairo Balart
2019-01-04dev, arm: Warn on PL011 DMA disableJan-Peter Larsson
2019-01-04dev-arm: Added VGIC GICV_IIDR responseAnouk Van Laer
2019-01-04dev-arm: Implement GIC-400 model from GicV2Giacomo Travaglini
2019-01-04dev-arm: Move VGic from Realview.py to Gic.pyGiacomo Travaglini
2019-01-04dev-arm: Added unimplemented GICv2 GICC_DIRAnouk Van Laer
2018-10-17dev-arm: Don't panic when EOIR a non active PPIAdrien Pesle
2018-10-17dev-arm: Fix Gicv2 distributor group registerAdrien Pesle
2018-10-12arm: Use little endian packet accessors.Gabe Black
2018-10-08dev, arm: remove the RealViewEB platformCiro Santilli
2018-10-01dev-arm: Enable FIQ signaling for Group0 interrupts in GICv2Giacomo Travaglini
2018-10-01dev-arm: Create postFiq events for GICv2Giacomo Travaglini
2018-10-01dev-arm: Implement GICv2 GICD_IGROUPR registerGiacomo Travaglini
2018-10-01dev-arm: Fix GICv2 cpu interrupt enable flagGiacomo Travaglini
2018-10-01dev-arm: Add basic support for level sensitive SPIs in GICv2Adrien Pesle
2018-09-28dev-arm: Make CpuLocalTimer use standard ArmInterruptPinGiacomo Travaglini
2018-09-28dev-arm: Take into account PPI enable bitGiacomo Travaglini
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