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2020-01-06dev-arm: GICv3, handle GICR_ICFGR0 WI behaviourAdrian Herrera
Architecture states write accesses to GICR_ICFGR0 are WI. This patch implements handling of this behaviour instead of crashing as an invalid offset. This is required to support certain software behaviour. Change-Id: I1f8c57838566c360d243a925306ec35c64a920b2 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24063 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-20configs: arm realview(64) regressions using VExpress_GEM5_V1Giacomo Travaglini
This patch is updating the arm regression configs so that the newer VExpress_GEM_V1 platform is used instead of the older VExpress_EMM and VExpress_EMM64. A new optional kernel_mode argument has been added in order to distinguish between realview and realview64 platforms. If not provided the config will assume the machine is running a AArch64 kernel. Other notable additions: - DTB autogeneration in regressions - Using minimal m5exit.squashfs disk image Change-Id: Ia230565f072fe3eb7756c41876dba4657583f4df Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22687 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-12-10dev-arm: GenericTimer, configurable base and low freqsAdrian Herrera
Architecture states the system counter has a fixed base frequency provided in the first entry of the frequency modes table. Optionally, other lower frequencies may be specified in consecutive entries. This patch adds configurable frequencies to the GenericTimer model. The default base frequency is kept as the one that was previously hardcoded for backwards compatibility. The table is not recommended to be updated once the system is running. Change-Id: Icba0b340a0eb1cbb47dfe7d7e03b547af4570c60 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22425 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10dev-arm: GenericTimer, freq as 32-bit valueAdrian Herrera
The System Counter frequency is now a 32-bit value. This is consistent with CNTFRQ and CNTFRQ_EL0 register sizes. Change-Id: I39886a3767adbe9c58887b8b6d5f30ebc6035bcc Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22424 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28dev-arm: Automatically assign PCI device ids in attachPciDeviceCiro Santilli
Simulation scripts currently need to assign PCI device addresses when adding new devices. This change moves this responsibility to the VExpress_GEM5_BASE::attachPciDevice method. Change-Id: I6d62af8a8f9176d964cc011dd8fb9744154bbb87 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22830 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-28dev-arm: device name in AmbaFake accessesAdrian Herrera
This patch prints the name of the AmbaFake device being accessed. This is useful for identifying the device triggering the warning. Change-Id: I69ca06d5d9bce73d918b8c8b46bb43e92597933b Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22847 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-25dev-arm: Adjust off_chip ranges in VExpress_GEM5 platformGiacomo Travaglini
This is need after commit b4c9996d894118be04cdf4ed793b35a1d5001942 which makes the AddrRange end address non inclusive. Change-Id: I859b84f6a91107815236b67c4596291c78881fe3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23003 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-20base,tests: Expanded GTests for addr_range.hhBrandon Potter
These tests assume the "end address" is not included in the range. This exposed some bugs in addr_range.hh which have been fixed. Where appropriate code comments in addr_range.hh have been extended to improve understanding of the class's behavior. Hard-coded AddrRange values in the project have been updated to take into account that end address is now exclusive. The python params.py interface has been updated to conform to this new standard. Change-Id: Idd1e75d5771d198c4b8142b28de0f3a6e9007a52 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22427 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-14arch-arm: Refactor code to check if gic is GicV2Chun-Chen TK Hsu
Refactor code to use cpu_addr only when gic is GicV2 since cpu_addr is only meanful to GicV2. Test: Boot Android P successfully with the following command: M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py --dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb --kernel $PWD/fs_files/binaries/vmlinux --disk $PWD/fs_files/disks/disk.img --kernel-init "/init" --cpu-type fastmodel --machine-type VExpressFastmodel --big-cpu-clock "2GHz" --big-cpus 1 --little-cpus 0 --mem-size 8GB --kernel-cmd "earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=8GB root=/dev/vda1 init=/init androidboot.hardware=gem5 qemu=1 qemu.gles=2 android.bootanim=0 vmalloc=640MB android.early.fstab=/fstab.gem5 androidboot.selinux=permissive audit=0 cma=128M" Change-Id: Iedd1388f292685c25f1effcd2e14b3db8899dff9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21339 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-11-14fastmodel: Add VExpressFastmodel platformChun-Chen TK Hsu
A VExpress based platform with FastModelGIC as interrupt controller. Change-Id: I5ef6d04573d271225d7b39c110e93350a290c371 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21359 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-05dev-arm: optional instantiation of GICv3 ITSAdrian Herrera
GICv3 ITS is an optional component of GICv3. The previous behaviour was for a stub ITS to be created by default, which resulted in a crash for use cases where a GICv3 with no ITS is required. This patch removes the instantiation of the ITS by default and adds checks for its presence both in initialization and device tree generation code. Change-Id: Id424924c8c1152d512aaa2837de4aa60329ec234 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22423 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-01dev-arm: Add SMMUv3 to VExpress_GEM5_V*Giacomo Travaglini
The VExpress_GEM5_V* Platforms will now optionally make use of the SMMUv3. In order to attach a devices to it, a user must simply use the attachSmmu method, making sure the device it is not part of the _on_chip_devices(). Change-Id: Ib819eb50d43dba1f5e5d1a1f7159ac4fbaccff6e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21559 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30dev: Get PageBytes from the system in the ARM generic timer.Gabe Black
These will ultimately by ArmISA::PageBytes, but this is more consistent with other devices which don't know what ISA they're part of. Change-Id: Iac13d5010564512207ed009377a771ee5949eff3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22269 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-30arm: Get rid of using namespace std and TheISA in realview.cc.Gabe Black
Neither was actually used by the nearly empty file. Change-Id: Ief1b77b18c8c616511bf9870e1667439a42dfcbd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22266 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-22configs: Clean setupBootLoader signatureGiacomo Travaglini
This is because the bus parameter is not used anymore Change-Id: I27aa8cc064904a6e3e0376f61eb7db74ea1a4d6c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22002 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-22dev-arm, configs: Using _on_chip_memory for on chip memoryGiacomo Travaglini
This patch is pulling the on-chip memory outside of the on_chip_devices list. The external interface will be more or less the same: configuration scripts will still use the attachOnChipIO method; a new kw argument has been added in order to store mem_ports. We want to provide to on-chip memory the same mechanism used when collecting on-chip dma ports. This is needed when using Ruby, since we need to pass a non None mem_ports to prevent the bootmem to be wired to the bus. Change-Id: Ifc519c3072dc5de1530772c70c80dc2094e2c54c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22000 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-18dev-arm: Check for gem5 extensions in GicV2Tiago Muck
Using GicV2 without setting the gem5_extensions parameter in a config with more than 8 is not allowed to prevent overflow of the 8-bit mask. Change-Id: I780c6985e8f44ed780b4f74f9a27805124e23a7b Signed-off-by: Tiago Mück <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19288 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-15dev-arm: Carve out a portion of VExpress_GEM5 for the bootloaderGiacomo Travaglini
This patch is carving out a portion of VExpress_GEM5 memory for the bootloader. Prior to this patch this was only happening conditionally/dynamically via the setupBootLoader call. With this patch the region is always present and the setupBootLoader doesn't instantiate memory, it is only setting up some bootloader parameters. Change-Id: Iaa5cdf471b14e8faa37353a25631bf7c6fc64afc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21604 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-10dev-arm, configs: Remove RealViewPBX platformGiacomo Travaglini
This is an old unused platform. We should support VExpress_GEM5 based platforms only. Change-Id: If9c29047b2d068992dfbbe0dc268c70b788cce5f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21601 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-02dev-arm: Improve fault message on SMMUv3 translation faultMarc Mari Barcelo
Change-Id: Ib1d7ae73951b52f2378f8bd50e804d3237f74074 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21303 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-02dev-arm: Fix address used to update the SMMUv3 Walk CacheMarc Mari Barcelo
Last level of SMMUv3 WalkCache should store the address without an offset. Change-Id: I1046bd8210500c2c38802acd41a4403e52fd3c90 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21302 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19dev-arm: Conditionally enable HDLcd when doing DTB autogenGiacomo Travaglini
This is a preparation change for a real DTB autogen implementation Change-Id: Ia0c1c5e65ea96036e55455eb4222cec12944d33a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20331 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19dev-arm: Add HDLcd DTB autogenerationGiacomo Travaglini
A Display has been defined. Its sole purpose is to generate the device tree node to be referenced by the HDLcd device. The encoder parameters are based on the existing node defined in: system/arm/dt/armv8.dts Change-Id: I6cdeb0437dce207dbd0f2c65c16b224245eb74e1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20330 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-16dev-arm: Allow IOMMU binding to HDLcdGiacomo Travaglini
Change-Id: I894080e7bd76e7efedef141c937e1561c0c0527c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20841 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-13dev-arm: Store the IOMMU reference from within the SMMU::connectGiacomo Travaglini
Change-Id: I35718a71dc040ee4acad9eee2a07076ebb571304 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20840 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-09dev-arm: Reset HPPI when clearing an LPIGiacomo Travaglini
Change-Id: I2a69e6cef69aa48d7c265d59915b859e5eac2bcc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20638 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Add resetHppi method in the GICv3 cpu interfaceGiacomo Travaglini
The method is used for resetting the highest priority pending interrupt interrupt from the cpu interface if it matches the intid passed as an argument. Change-Id: I9fbc4cb3e05a1cc32f853b6afab5c2bc99369435 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20637 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Cleanup GICv3 initializationGiacomo Travaglini
This patch is removing the unnecessary initState() / reset() methods from GICv3 classes, since we can initialize everything at construction/init time Change-Id: Ia70edcc4ca4f11878fac0024342e4f2cd81883a0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20636 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Initialize GICD_TYPER once at construction timeGiacomo Travaglini
Change-Id: Ib4dfdf7005709c22b4ba95099b1192f6edd6ff06 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20635 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Writes to IGRPEN1_EL3 triggering updateGiacomo Travaglini
Change-Id: I56804eb1bfc8913bd0d3cab05865a382bf270bc1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20634 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Fix GICv3 ITS cmdq wrappingGiacomo Travaglini
Change-Id: I979e8d1378d5b5d2647158798479cf4238f2c349 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20633 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1Giacomo Travaglini
Previous mapping was wrong because it was checking which security bits it was accessing by using the inSecureState() function, whereas it should have used the isSecureBelowEL3(). This patch is not making the sostitution since it is optimizing the mapping furthermore by avoiding updating both IGRPEN1_EL1 and IGRPEN1_EL3 on writes. The IGRPEN1_EL1 register is used as a storage, and any reads/writes to IGRPEN1_EL3 is routed to that register. Change-Id: Id318ec44e19d4f844e4e3410d74d0c4f89810811 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20632 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Implement message-based SPIsGiacomo Travaglini
Change-Id: I35e79dfd572c3e0d9cadc8e0aab01befd6004ece Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20631 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev: Scrub out some lingering uses of MemObject.Gabe Black
MemObject doesn't do anything any more, and is basically just an alias for ClockedObject. Change-Id: Ic0e1658609e4e1d7f4b829fbc421f222e4869dee Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20719 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-07dev-arm: Add GICD_SGIR registerGiacomo Travaglini
The Distributor Software Generated Interrupt Register is implemented only if affinity routing is disabled. Since this configuration is currently not supported in gem5, it has to be treated as RES0. Change-Id: I9ffcb31b26fc17547f74a4f1d43ce72c59786fa8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20630 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-06dev-arm: State update when setting MISCREG_ICC_IGRPENx registerGiacomo Travaglini
This is because by enabling ainterrupt group at the cpu interface, we need to check if a previously pending interrupt needs to be forwarded to the PE. We are doing the same when globally enabling irqs in the distributor (GICD_CTLR). Change-Id: I80aeb87b2a58a108de899006d5a2f12eadbe6c2e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20629 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ic08ac1e7f3ebef408a83aa068ce15e9dfe2aa3cd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20628 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ide93464f62288fbe8f409f718487a15512c01295 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20627 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Add read/writeBanked helpers to GICv3Giacomo Travaglini
These will be used by AA64 security banked registers in GICv3. Change-Id: Ia980c4f5c14187ab9c18da1d1d596562644111ae Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20624 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Rewrite ICC_BPR0/ICC_BPR1 handlingGiacomo Travaglini
The patch is fixing BPR reads in AA32, by removing the line Gicv3::GroupId group = misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S; Where a read to ICC_BPR0 will return a G1S group. The patch is also fixing Security banking accesses. Change-Id: I28f1d1244c44d4b8b202d3141f8380943c7c1c86 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20620 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Add GICv3 unimplemented Hyp Active Priorities Group regsGiacomo Travaglini
ICH_APxR1, ICH_APxR2, ICH_APxR3 are implemented only if supporting more than 6 bits of priority. Since this is not the case, they are currently unimplemented. According to spec, unimplemented registers are RAZ/WI. Change-Id: Ifd7f7a3d42b4575c2f7aff3b95d5a47ac1e61842 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20619 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Allow 32-bit access to GITS_TYPERGiacomo Travaglini
Change-Id: I9d19174b38ba70f82050102f955ccc162965d1fb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20618 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Cpu interface groupEnabled check for global enableGiacomo Travaglini
Gicv3CPUInterface::groupEnabled should check for global enable flags at distributor level: - Gicv3Distributor.EnableGrp0 - Gicv3Distributor.EnableGrp1S - Gicv3Distributor.EnableGrp1NS Change-Id: I1c855b0e4c2bc8f1cd0a8f086b9450f516177b08 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20617 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Check if INTID group is enabled when reading HPPIRxGiacomo Travaglini
If it is not enabled, it should return INTID_SPOURIOUS Change-Id: I4dfa8b9fcea874b4d281cd154dd38752b05e1d59 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20616 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Writing GICD_CTLR should trigger an updateGiacomo Travaglini
This is the case where an interrupt is pending, but the distributor is masking it. As soon as the group gets enabled, the interrupt should be forwarded to the PE. Change-Id: Ie428780bde7e4726688adf78dfcc4d43d1b45261 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20615 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Rewrite GICv3 updateGiacomo Travaglini
The GICv3 update methods are method which are invoked anytime the model needs to evaluate a change in its state, which most of the time means managing the state of an interrupt (forwarding it to a PE, deasserting it, etc). The way it is currently done is a little bit obscure and doesn't handle correctly IRQ prioritization. Example: An IRQ which is handled by the redistributor (PPI or LPI) was not competing with any pending interrupts coming from the distributor (SPIs) once raised by a peripheral. Also the way the pending state of an interrupt was removed at the cpu interface level wasn't happening in place where this was actually happening (E.g. when activating it), but happened with a weird fullUpdate semantic, where if there was a pending interrupt in a cpu interface, all cpu interfaces had their pending interrupt (if any) been disabled. With this patch, state update always starts at the distributor, and it goes down until the cpu interface where a Gicv3CPUInterface::update method selects the winning interrupt coming from distributor/redistributor to be forwarded to the PE. Change-Id: I1c517cbc4bf107cc2d7ae7beb2692e3cf5187a40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20614 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Fix GICv3 IGRPMOD writesGiacomo Travaglini
Writes to IGRPMOD were not right shifting the value, which resulted in interrupts having a IGRPMOD value > 1, whereas the only allowed values are 0 and 1. Change-Id: Id491bd1b184d6e5abeeea25ea272eeb91792ccf7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20613 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Fix SGI generationGiacomo Travaglini
The patch is fixing the following aspects of SGIs * The conditons over which an SGI can be forwarded to a PE * SGIs in AArch32 (see below) It is in fact refactoring SGI generation under a common method in the cpu interface. It is abandoning the implicit fallthrough mechanism not only for cosmetic reasons, but also because checking "misc_reg ==" was only working if the register was an AArch64 one (e.g. MISCREG_ICC_SGI0R_EL1) and not the AArch32 counterpart (MISCREG_SGI0R). Change-Id: I6fedfb80388666f4f1d20f6abef378a9f093aa83 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20610 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Gicv3 ITS device tree autogenAdrian Herrera
This patch adds device tree automatic generation for Gicv3 ITS. Change-Id: Ic01500ffa691b331f527c5c2c785ff715660b0c2 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20609 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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