summaryrefslogtreecommitdiff
path: root/src/dev/arm
AgeCommit message (Expand)Author
2019-10-30dev: Get PageBytes from the system in the ARM generic timer.Gabe Black
2019-10-30arm: Get rid of using namespace std and TheISA in realview.cc.Gabe Black
2019-10-22configs: Clean setupBootLoader signatureGiacomo Travaglini
2019-10-22dev-arm, configs: Using _on_chip_memory for on chip memoryGiacomo Travaglini
2019-10-18dev-arm: Check for gem5 extensions in GicV2Tiago Muck
2019-10-15dev-arm: Carve out a portion of VExpress_GEM5 for the bootloaderGiacomo Travaglini
2019-10-10dev-arm, configs: Remove RealViewPBX platformGiacomo Travaglini
2019-10-02dev-arm: Improve fault message on SMMUv3 translation faultMarc Mari Barcelo
2019-10-02dev-arm: Fix address used to update the SMMUv3 Walk CacheMarc Mari Barcelo
2019-09-19dev-arm: Conditionally enable HDLcd when doing DTB autogenGiacomo Travaglini
2019-09-19dev-arm: Add HDLcd DTB autogenerationGiacomo Travaglini
2019-09-16dev-arm: Allow IOMMU binding to HDLcdGiacomo Travaglini
2019-09-13dev-arm: Store the IOMMU reference from within the SMMU::connectGiacomo Travaglini
2019-09-09dev-arm: Reset HPPI when clearing an LPIGiacomo Travaglini
2019-09-09dev-arm: Add resetHppi method in the GICv3 cpu interfaceGiacomo Travaglini
2019-09-09dev-arm: Cleanup GICv3 initializationGiacomo Travaglini
2019-09-09dev-arm: Initialize GICD_TYPER once at construction timeGiacomo Travaglini
2019-09-09dev-arm: Writes to IGRPEN1_EL3 triggering updateGiacomo Travaglini
2019-09-09dev-arm: Fix GICv3 ITS cmdq wrappingGiacomo Travaglini
2019-09-09dev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1Giacomo Travaglini
2019-09-09dev-arm: Implement message-based SPIsGiacomo Travaglini
2019-09-09dev: Scrub out some lingering uses of MemObject.Gabe Black
2019-09-07dev-arm: Add GICD_SGIR registerGiacomo Travaglini
2019-09-06dev-arm: State update when setting MISCREG_ICC_IGRPENx registerGiacomo Travaglini
2019-09-06arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06dev-arm: Add read/writeBanked helpers to GICv3Giacomo Travaglini
2019-09-06dev-arm: Rewrite ICC_BPR0/ICC_BPR1 handlingGiacomo Travaglini
2019-09-06dev-arm: Add GICv3 unimplemented Hyp Active Priorities Group regsGiacomo Travaglini
2019-09-06dev-arm: Allow 32-bit access to GITS_TYPERGiacomo Travaglini
2019-09-06dev-arm: Cpu interface groupEnabled check for global enableGiacomo Travaglini
2019-09-06dev-arm: Check if INTID group is enabled when reading HPPIRxGiacomo Travaglini
2019-09-06dev-arm: Writing GICD_CTLR should trigger an updateGiacomo Travaglini
2019-09-06dev-arm: Rewrite GICv3 updateGiacomo Travaglini
2019-09-06dev-arm: Fix GICv3 IGRPMOD writesGiacomo Travaglini
2019-09-06dev-arm: Fix SGI generationGiacomo Travaglini
2019-09-06dev-arm: Gicv3 ITS device tree autogenAdrian Herrera
2019-09-06dev-arm: modify GICv3 ITS default addrAdrian Herrera
2019-09-05dev-arm: Improper translation slot release in SMMUv3Giacomo Travaglini
2019-09-05dev-arm: Implement invalidateASID in SMMUv3 WalkCacheJan-Peter Larsson
2019-09-05dev-arm: Implement invalidateVA/VAA in SMMUv3 WalkCacheAdrian Herrera
2019-08-27cpu, dev, mem: Use the new Port methods.Gabe Black
2019-08-26dev-arm: Fix GICv3 ITS indexing errorGiacomo Travaglini
2019-08-26dev-arm: Fix GITS_BASER initialization/accessGiacomo Travaglini
2019-08-22dev-arm: Start using GITS_CTLR.quiescent bitGiacomo Travaglini
2019-08-22dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR/BASER)Giacomo Travaglini
2019-08-22dev-arm,system-arm: missing GICv3 ranges propertyAdrian Herrera
2019-08-20dev-arm: Add redistributor-stride property to GICv3Giacomo Travaglini
2019-08-20dev-arm: Add GITS_PIDR2 register to the ITS memory mapGiacomo Travaglini
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 03:04:41 +0000