| Age | Commit message (Collapse) | Author |
|---|
|
The aforementioned registers (Interrupt Processor Targets Registers) are
banked per-CPU, but are read-only. This patch eliminates the per-CPU
storage of these values that are simply computed.
Change-Id: I52cafc2f58e87dd54239a71326c01f4923544689
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2442
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
|
|
Change-Id: I696703418506522ba90df5c2c4ca45c95a6efbea
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2441
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
|
|
The generic timer sometimes needs to access global state. This can
lead to race conditions when simulating a multi-core KVM system where
each core lives in its own thread. In that case, the setMiscReg and
readMiscReg methods are called from the thread owning the CPU and not
the global device thread.
Change-Id: Ie3e982258648c8562cce0b30a0c122dfbfaf42cd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2460
Reviewed-by: Weiping Liao <weipingliao@google.com>
|
|
Change-Id: I4c0de7c2a5b40c1a9f009ca12062cb108b450b04
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
The Pl390::getAddrRanges() method should have been flagged using the
override keyword. Other methods in this class already use the override
keyword, so this results in a warning about inconsistent override
usage when compiling using clang.
Change-Id: I17449687a8e074262232562487b58c96466bd54e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
The GIC model currently adds a delay to interrupts when posting them
to a target CPU. This means that an interrupt signal will be
represented by an event for a short period of time. We currently
ignore this when draining and serialize the tick when the interrupt
will fire. Upon loading the checkpoint, the simulated GIC reschedules
the pending events. This behaviour is undesirable when we implement
support for switching between in-kernel GIC emulation and gem5 GIC
emulation. In that case, the (kernel) GIC model gets a lot simpler if
we don't need to worry about in-flight interrupts from the gem5 GIC.
This changeset adds a draining check to force the GIC into a state
where all interrupts have been delivered prior to checkpointing/CPU
switching. It also removes the now redundant serialization of
interrupt events.
Change-Id: I8b8b080aa291ca029a3a7bdd1777f1fcd5b01179
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2331
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
|
|
Lots of minor cleaups:
* Make cached params const
* Don't serialize params
* Use AddrRange to represent the distributor and CPU address spaces
* Store a const AddrRangeList of all PIO ranges
Change-Id: I40a17bc3a38868fb3b8af247790e852cf99ddf1d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2330
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
|
|
Use the new fast scan-out API in the PixelPump to render frames at a
fixed frame rate in KVM mode. The refresh rate when running in KVM can
be controlled by the virt_refresh_rate parameter.
Change-Id: Ib3c78f174e3f8f4ca8a9b723c4e5d311a433b8aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2242
Reviewed-by: Rahul Thakur <rjthakur@google.com>
|
|
Add a helper function to scan out an entire frame in one time
step. This requires the public PixelPump to be changed somewhat to
separate timing updates from general PixelPump control. Instead of
calling PixelPump::start(timings), timings now need to be updated
using a separate call to PixelPump::updateTimings(timings) before
calling PixelPump::start().
Display controllers that don't need accurate timing (e.g., in KVM
mode), can use the new PixelPump::renderFrame() API to render an
entire frame in one step. This call results in the same callbacks
(e.g., calls to nextPixel()) as the timing calls, but they all happen
in immediately. Unlike the timing counterpart, renderFrame() doesn't
support buffer underruns and will panic if nextPixle() indicates an
underrun.
Change-Id: I76c84db04249b02d4207c5281d82aa693d0881be
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2241
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
|
|
Added functionality to check and clear interrupts for KMI
devices. This fixes a boot bug when using KVM and in-kernel GIC
emulation.
Change-Id: Ia3e91d07567b7faf3f82b0adfda4a165a502a339
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2225
Reviewed-by: Rahul Thakur <rjthakur@google.com>
|
|
Automatically use the MuxingKvmGic in the VExpress_GEM5_V1
platform. This removes the need to patch the host kernel or the
platform configuration when using KVM on ARM.
Change-Id: Ib1ed9b3b849b80c449ef1b62b83748f3f54ada26
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
|
|
Change-Id: Ifc65d42eebfd109c1c622c82c3c3b3e523819e85
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Used cppclean to help identify useless includes and removed them. This
involved erroneously included headers, but also cases where forward
declarations could have been used rather than a full include.
|
|
|
|
Improve PL011 console interactivity
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
|
|
The generic timer needs a pointer to an ArmSystem to wire itself to the
system register handler. This was previously specified as an instance
of System that was later cast to ArmSystem. Make this more robust by
specifying it as an ArmSystem in the Python interface and add a check
to make sure that it is non-NULL.
Change-Id: I989455e666f4ea324df28124edbbadfd094b0d02
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
|
|
Change-Id: If19b9c593b48ded1ea848f2d3710d4369ec8a221
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Add a customizable NoMali GPU model and an example Mali T760
configuration. Unlike the normal NoMali model (NoMaliGpu), the
NoMaliCustopmGpu model exposes all the important GPU ID registers to
Python. This makes it possible to implement custom GPU configurations
by without changing the underlying NoMali library.
Change-Id: I4fdba05844c3589893aa1a4c11dc376ec33d4e9e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
|
|
When using a Ruby memory system, the Ruby configuration scripts expect
to get a list of DMA ports to create the necessary DMA sequencers. Add
support in the utility functions that wire up devices to append DMA
ports to a list instead of connecting them to the IO bus. These
functions are currently only used by the VExpress_GEM5_V1 platform.
Change-Id: I46059e46b0f69e7be5f267e396811bd3caa3ed63
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
|
|
The boot ROM shouldn't be used as a memory by the kernel. Memories
have a flag to indicate this which is set for some platforms. Update
all platforms to consistently set this flag to indicate that the boot
ROM shouldn't be reported as normal memory.
Change-Id: I2bf0273e99d2a668e4e8d59f535c1910c745aa7b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
--HG--
extra : amend_source : c2cbda38636ea37cbe9ae6977a06b923eab5ba56
|
|
Factored out of the larger banked register change.
Change-Id: I947dbdb9c00b4678bea9d4f77b913b7014208690
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Updated according to GICv2 documentation.
Change-Id: I5d926d1abf665eecc43ff0f7d6e561e1ee1c390a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Fixing an issue with regStats not calling the parent class method
for most SimObjects in Gem5. This causes issues if one adds new
stats in the base class (since they are never initialized properly!).
Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Make it possible to disable gem5 gic extensions by setting the
gem5_extensions param to False from Python.
Change-Id: Icb255105925ef49891d69cc9fe5cc55578ca066d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Geoffrey Blake <geoffrey.blake@arm.com>
|
|
As identified by clang-3.8, there was a superfluous loop increment in
the flash device which is now removed.
Change-Id: If46a1c4f72d3d4c9f219124030894ca433c790af
Reviewed-by: Rene De Jong <rene.dejong@arm.com>
|
|
Given we do not simulate a FIFO currently there are only two states
we can be in upon read: empty or full. Properly signal the latter.
Add and sort constants for states in the header file.
Committed by Jason Lowe-Power <power.jg@gmail.com>
|
|
The GICv2 has a new and slightly more consistent register
naming. Update gem5's GIC register names to match the new
documentation.
Change-Id: I8ef114eee8a95bf0b88b37c18a18e137be78675a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
|
|
|
|
Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.
Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.
Add dump call back function to allow stats update of distribution and residency
stats.
|
|
This patch enables Linux to read the temperature using hwmon infrastructure.
In order to use this in your gem5 you need to compile the kernel using the
following configs:
CONFIG_HWMON=y
CONFIG_SENSORS_VEXPRESS=y
And a proper dts file (containing an entry such as):
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
temp@0 {
compatible = "arm,vexpress-temp";
arm,vexpress-sysreg,func = <4 0>;
label = "DCC";
};
};
|
|
This changeset adds support for changing the simulator output
directory. This can be useful when the simulation goes through several
stages (e.g., a warming phase, a simulation phase, and a verification
phase) since it allows the output from each stage to be located in a
different directory. Relocation is done by calling core.setOutputDir()
from Python or simout.setOutputDirectory() from C++.
This change affects several parts of the design of the gem5's output
subsystem. First, files returned by an OutputDirectory instance (e.g.,
simout) are of the type OutputStream instead of a std::ostream. This
allows us to do some more book keeping and control re-opening of files
when the output directory is changed. Second, new subdirectories are
OutputDirectory instances, which should be used to create files in
that sub-directory.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Add a callback handler for the NoMali reset callback. This callback is
called whenever the GPU is reset using the register interface or the
NoMali API. The callback can be used to override ID registers using
the raw register API.
|
|
Refactor and cleanup the NoMaliGpu class:
* Use a std::map instead of a switch block to map the parameter enum
describing the GPU type to a NoMali type.
* Remove redundant NoMali handle from the interrupt callback.
* Make callbacks and API wrappers protected instead of private to
enable future extensions.
* Wrap remaining NoMali API calls.
|
|
Result of running 'hg m5style --skip-all --fix-control -a'.
|
|
Add a platform with support for both aarch32 and aarch64. This
platform implements a subset of the devices in a real Versatile
Express and extends it with some gem5-specific functionality. It is in
many ways similar to the old VExpress_EMM64 platform, but supports the
following new features:
* Automatic PCI interrupt assignment
* PCI interrupts allocated in a contiguous range.
* Automatic boot loader selection (32-bit / 64-bit)
* Cleaner memory map where gem5-specific devices live in CS5 which
isn't used by current Versatile Express platforms.
* No fake devices. Devices that were previously faked will be
removed from the device tree instead.
* Support for 510 GiB contiguous memory
|
|
Add support for automatic PCI interrupt routing using a device's ID on
the PCI bus. Our current DTBs typically tell the kernel that we do
this or something similar when declaring the PCI controller. This
changeset adds an option to make the simulator behave in the same way.
Interrupt routing can be selected by setting the int_policy parameter
in the GenericArmPciHost. The following values are supported:
* ARM_PCI_INT_STATIC: Use the old static routing policy using the
interrupt line from a device's configurtion space.
* ARM_PCI_INT_DEV: Use device number on the PCI bus to map to an
interrupt in the GIC. The interrupt is computed as:
gic_int = int_base + (pci_dev % int_count)
* ARM_PCI_INT_PIN: Use device interrupt pin on the PCI bus to map to
an interrupt in the GIC. The PCI specification reserves pin ID 0
for devices without interrupts, the interrupt therefore computed
as:
gic_int = int_base + ((pin - 1) % int_count)
|
|
Make best use of the compiler, and enable -Wextra as well as
-Wall. There are a few issues that had to be resolved, but they are
all trivial.
|
|
Move the IDE controller and the disk implementations to
src/dev/storage.
--HG--
rename : src/dev/DiskImage.py => src/dev/storage/DiskImage.py
rename : src/dev/Ide.py => src/dev/storage/Ide.py
rename : src/dev/SimpleDisk.py => src/dev/storage/SimpleDisk.py
rename : src/dev/disk_image.cc => src/dev/storage/disk_image.cc
rename : src/dev/disk_image.hh => src/dev/storage/disk_image.hh
rename : src/dev/ide_atareg.h => src/dev/storage/ide_atareg.h
rename : src/dev/ide_ctrl.cc => src/dev/storage/ide_ctrl.cc
rename : src/dev/ide_ctrl.hh => src/dev/storage/ide_ctrl.hh
rename : src/dev/ide_disk.cc => src/dev/storage/ide_disk.cc
rename : src/dev/ide_disk.hh => src/dev/storage/ide_disk.hh
rename : src/dev/ide_wdcreg.h => src/dev/storage/ide_wdcreg.h
rename : src/dev/simple_disk.cc => src/dev/storage/simple_disk.cc
rename : src/dev/simple_disk.hh => src/dev/storage/simple_disk.hh
|
|
Previous ARM-based simulations were limited to 8 cores due to
limitations in GICv2 and earlier. This changeset adds a set of
gem5-specific extensions that enable support for up to 256 cores.
When the gem5 extensions are enabled, the GIC uses CPU IDs instead of
a CPU bitmask in the GIC's register interface. To OS can enable the
extensions by setting bit 0x200 in ICDICTR.
This changeset is based on previous work by Matt Evans.
|
|
The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).
This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.
PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.
The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.
Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:
* Configurable configuration space decoding. The number of bits
dedicated to a device is a prameter, making it possible to support
both CAM, ECAM, and legacy mappings.
* Basic interrupt mapping using the interruptLine value from a
device's configuration space. This behavior is the same as in the
old implementation. More advanced controllers can override the
interrupt mapping method to dynamically assign host interrupts to
PCI devices.
* Simple (base + addr) remapping from the PCI bus's address space to
physical addresses for PIO, memory, and DMA.
|
|
The HDLCD model implements a workaround that swaps the red and blue
channels. This works around an issue in certain old kernels. The new
driver doesn't seem to have this behavior, so disable the workaround
by default and enable it in the affected platforms.
|
|
Devices behind the Versatile Express configuration controllers are
currently all lumped into one SimObject. This will make DTB generation
challenging since the DTB assumes them to be in different parts of the
hierarchy. It also makes it hard to model other CoreTiles without also
replicating devices from the motherboard.
This changeset splits the VExpressCoreTileCtrl into two subsystems:
VExpressMCC for all motherboard-related devices and CoreTile2A15DCC
for Core Tile specific devices.
|
|
The flash model has typos in its serialization code for
unknownPages, locationTable, blockValidEntries, and blockEmptyEntries
arrays where it would save each entry in the array under the same
name in the checkpoint. This patch fixes these typos.
|
|
The IICRPR register in the GIC is currently not being initialized when
the GIC is instantiated. Initialize to the value mandated by the
architecture specification.
|
|
Fix a bug in which the flash device would write out of bounds and
could either trigger a segfault and corrupt the memory of other
objects. This was caused by using pageSize in the place of
pagesPerBlock when running the garbage collector.
Also, added an assert to flag this condition in the future.
|
|
This patch fixes the drain logic for the UFSHostDevice and the
FlashDevice. In the case of the FlashDevice, the logic for CheckDrain
needed to be reversed, whilst in the case of the UFSHostDevice check
drain was never being called. In both cases the system would never
complete draining if the initial attampt to drain failed.
|
|
Make clang >= 3.5 happy when compiling build/ARM/gem5.opt on OSX.
|
|
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
|
|
Add a stat that counts buffer underruns in the HDLCD controller. The
stat counts at most one underrun per frame since the controller aborts
the current frame if it underruns.
|
|
Rewrite the HDLCD controller to use the new DMA engine and pixel
pump. This fixes several bugs in the current implementation:
* Broken/missing interrupt support (VSync, underrun, DMA end)
* Fragile resolution changes (changing resolutions used
to cause assertion errors).
* Support for resolutions with a width that isn't divisible by 32.
* The pixel clock can now be set dynamically.
This breaks checkpoint compatibility. Checkpoints can be upgraded with
the checkpoint conversion script. However, upgraded checkpoints won't
contain the state of the current frame. That means that HDLCD
controllers restoring from a converted checkpoint immediately start
drawing a new frame (i.e, expect timing differences).
|
