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2017-11-17sim: Implement load_addr_mask auto-calculationGeoffrey Blake
Recent Linux kernels for AArch64 have changed their start addresses but we still want to relocate the kernel to 0x80080000 which required hacking the load_addr_mask in Realview.py to be 0x7ffffff from 0xfffffff to mask off the proper number of MSBs to load the kernel in the desired location. To avoid having to make this change in the future again, we auto-calculate the load_addr_mask if it is specified as 0x0 in the System sim-object to find the most restrictive address mask instead of having the configuration specify it. If the configuration does specify the address mask, we use it instead of auto-calculating. Change-Id: I18aabb5d09945c6e3e3819c9c8036ea24b6c35cf Signed-off-by: Geoffrey Blake <Geoffrey.Blake@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2323 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-11-08dev: Move generic serial devices to src/dev/serialAndreas Sandberg
Change-Id: I104227fc460f8b561e7375b329a541c1fce881b2 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4291 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-11-08dev: Refactor UART->Terminal interfaceAndreas Sandberg
The UART models currently assume that they are always wired to a terminal. While true at the moment, this isn't necessarily a valid assumption. This change introduces the SerialDevice class that defines the interface for serial devices. Currently, Terminal is the only class that implements this interface. Change-Id: I74fefafbbaf5ac1ec0d4ec0b5a0f4b246fdad305 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4289 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-10-31dev: Using Configurable image writer in HDLcdGiacomo Travaglini
The fixed image writer (which was dumping .bmp images only) has been replaced by the configurable one in HDLcd device. Default format is Auto, which gives gem5 the freedom to choose the format it prefers. Change-Id: I0643266556bb10b43cdebd628f6daa2cd5e105dd Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5183 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-31base: Introducing utility for writing raw data in png formatGiacomo Travaglini
Originally it was possible to use a Bitmap writer class for dumping a framebuffer snapshot in a .bmp file. This patch enables you to choose another format. In particular it implements the writing of PNG Images using libpng library. The latter has to be already installed in your machine, otherwise gem5 will default to the Bitmap format. This configurable writer has been introduced in the VNC frame dumping mechanism, which is storing changed frame buffers from the VNC server Change-Id: Id7e5763c82235f1ce90381c8486b85a7cce734ce Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5181 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-01kvm, arm: Switch to the device EQ when accessing ISA devicesAndreas Sandberg
ISA devices typically run in the device event queue. Previously, we assumed that devices would perform their own EQ migrations as needed. This isn't ideal since it means we have different conventions for IO devices and ISA devices. Switch to doing migrations in the KVM CPU instead to make the behavior consistent. Change-Id: I33b74480fb2126b0786dbdbfdcfa86083384250c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4288 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-12arm: Refactor some Event subclasses to lambdasSean Wilson
Change-Id: Ic59add8afee1d49633634272d9687a4b1558537e Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3929 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-10dev-arm: Add ID registers to the GIC modelJose Marinho
Implement GICD_IIDR, GICC_IIDR, GICD_PIDR0, GICD_PIDR1, GICD_PIDR2, and GICD_PIDR3. Change-Id: I4f6b5a6303907226e7d8e2f677543b3868c02e7b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3961
2017-07-10dev-arm: Don't unconditionally overwrite bootloader paramsJose Marinho
The bootloader arguments were previously defaulting to a predetermined value even if initialized elsewhere in the platform config script. This commit fixes this issue by not calling the default initialization routine if the bootloader is already defined. Change-Id: Id80af4762b52dc036da29430b2795bb30970a349 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3967
2017-07-07kvm, arm: don't create interrupt events while saving GIC stateCurtis Dunham
If an interrupt was pending according to Kvm state during a drain, the Pl390 model would create an interrupt event that could not be serviced, preventing the system from draining. The proper behavior is for the Pl390 not actively being used for simulation to just skip the GIC state machine that delivers interrupts. Change-Id: Icb37e7e992f1fb441a9b3a26daa1bb5a6fe19228 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3661 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-05dev,arm: add Kvm mode of operation for CP15 timerCurtis Dunham
The timer device exposed via the ARM ISA, also known as the "CP15 timer" due to its legacy coprocessor encodings, is implemented by the GenericTimerISA class. During Kvm execution, however, this functionality is directly emulated by the hardware. This commit subclasses the GenericTimer, which is (solely) used by GenericTimerISA, to facilitate Kvm in much the same way as the prior GIC changes: the gem5 model is used as the backing store for state, so checkpointing and CPU switching work correctly, but isn't used during Kvm execution. The added indirection prevents the timer device from creating events when we're just updating its state, but not actually using it for simulation. Change-Id: I427540d11ccf049c334afe318f575146aa888672 Reviewed-on: https://gem5-review.googlesource.com/3542 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-05dev,arm: remove and recreate timer events around drainsCurtis Dunham
Having timer events stored in checkpoints complicates Kvm execution. We change the timer behavior so that it always deschedules any pending events on a drain() and recreates them on a drainResume(), thus they will never appear in checkpoints henceforth. This pattern of behavior makes it simpler to handle Kvm execution, where the hardware performs the timer function directly. Change-Id: Ia218868c69350d96e923c640634d492b5c19cd3f Reviewed-on: https://gem5-review.googlesource.com/3541 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-29arm: Fix memleak in Pl390 by adding destructorSean Wilson
Change-Id: I3395e64311f6aa7bbfb6eee9bfec82e832bcbd4d Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3901 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-29arm: Fix memleak in VGic by adding destructorSean Wilson
Change-Id: I864b5d9ed655cc52e440e2eb54987e8ff9a73296 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3900 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-20dev: Replace EventWrapper use with EventFunctionWrapperSean Wilson
Change-Id: I6b03cc6f67e76dffb79940431711ae6171901c6a Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3748 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-20arm: Replace EventWrapper use with EventFunctionWrapperSean Wilson
Change-Id: I08de5f72513645d1fe92bde99fa205dde897e951 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3747 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-19arm: ignore writes to the reset_ctl registerGedare Bloom
Change-Id: I953521572e6ace475b656369c9f07ddfa50d731a Signed-off-by: Gedare Bloom <gedare@rtems.org> Reviewed-on: https://gem5-review.googlesource.com/3263 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-19dev, arm: add a9mpcore global timer deviceGedare Bloom
Change-Id: I6d8a5e3795291b2a4cce022f555cf4b04f997538 Signed-off-by: Gedare Bloom <gedare@rtems.org> Reviewed-on: https://gem5-review.googlesource.com/3262 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-13arm: Refactor the VExpress_EMM system creationNikos Nikoleris
Change-Id: Iac3d15719b2bbc426020a27d6b47a4baaab078c7 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2907 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-03config: Adjust load_addr_mask in VExpress_GEM5_V1Weiping Liao
Fix load_addr_mask in VExpress_GEM5_V1 in order to boot with the 64-bit kernel. Change-Id: I13a0a752c60e53262a245cb24b16606071041397 Reviewed-on: https://gem5-review.googlesource.com/3643 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-31dev, arm: ignore writes to the SCUGedare Bloom
Change-Id: I31808b6d7ca2bc2af41deaec747e3a13bd4f77d2 Signed-off-by: Gedare Bloom <gedare@rtems.org> Reviewed-on: https://gem5-review.googlesource.com/3261 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-15arm, dev: stub out GIC distributor interrupt groupsCurtis Dunham
We don't implement the GICD_IGROUPRn registers, which is allowed, but to be correct, they should be RAZ/WI (read as zero, writes ignored). Change-Id: I8039baf72f45c0095f41e165b8e327c79b1ac082 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2620 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-09arm: Enable m5ops by default for VExpress_GEM5_V1Andreas Sandberg
Allocate 0x10010000-0x1001ffff for m5 pseudo-ops. This range is a part of the CS5 address range in the RS1/RS2 memory map. Change-Id: Ica45cd53bc4ebb62966afa099fa465e27fb0452c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2965
2017-04-03arm, kvm: implement GIC state transferCurtis Dunham
This also allows checkpointing of a Kvm GIC via the Pl390 model. Change-Id: Ic85d81cfefad630617491b732398f5e6a5f34c0b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2444 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm, dev: add basic support for GICC_BPR registerCurtis Dunham
The Binary Point Register (BPR) specifies which bits belong to the group priority field (which are used for preemption) and which to the subpriority field (which are ignored for preemption). Change-Id: If51e669d23b49047b69b82ab363dd01a936cc93b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2443 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handlingCurtis Dunham
The aforementioned registers (Interrupt Processor Targets Registers) are banked per-CPU, but are read-only. This patch eliminates the per-CPU storage of these values that are simply computed. Change-Id: I52cafc2f58e87dd54239a71326c01f4923544689 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2442 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm: refactor packet processing in Pl390 GICCurtis Dunham
Change-Id: I696703418506522ba90df5c2c4ca45c95a6efbea Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2441 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03dev, arm: Fix multi-core KVM race in the generic timerAndreas Sandberg
The generic timer sometimes needs to access global state. This can lead to race conditions when simulating a multi-core KVM system where each core lives in its own thread. In that case, the setMiscReg and readMiscReg methods are called from the thread owning the CPU and not the global device thread. Change-Id: Ie3e982258648c8562cce0b30a0c122dfbfaf42cd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2460 Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-03-21arm: correct register read bug in Pl390 GICCurtis Dunham
Change-Id: I4c0de7c2a5b40c1a9f009ca12062cb108b450b04 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-15arm, dev: Add missing override in the Pl390 GIC modelAndreas Sandberg
The Pl390::getAddrRanges() method should have been flagged using the override keyword. Other methods in this class already use the override keyword, so this results in a warning about inconsistent override usage when compiling using clang. Change-Id: I17449687a8e074262232562487b58c96466bd54e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-13dev, arm: Add draining to the GIC modelAndreas Sandberg
The GIC model currently adds a delay to interrupts when posting them to a target CPU. This means that an interrupt signal will be represented by an event for a short period of time. We currently ignore this when draining and serialize the tick when the interrupt will fire. Upon loading the checkpoint, the simulated GIC reschedules the pending events. This behaviour is undesirable when we implement support for switching between in-kernel GIC emulation and gem5 GIC emulation. In that case, the (kernel) GIC model gets a lot simpler if we don't need to worry about in-flight interrupts from the gem5 GIC. This changeset adds a draining check to force the GIC into a state where all interrupts have been delivered prior to checkpointing/CPU switching. It also removes the now redundant serialization of interrupt events. Change-Id: I8b8b080aa291ca029a3a7bdd1777f1fcd5b01179 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2331 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-13arm: Clean up the GIC implementationAndreas Sandberg
Lots of minor cleaups: * Make cached params const * Don't serialize params * Use AddrRange to represent the distributor and CPU address spaces * Store a const AddrRangeList of all PIO ranges Change-Id: I40a17bc3a38868fb3b8af247790e852cf99ddf1d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2330 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-07dev, arm: Render HDLCD frames at a fixed rate in KVMSudhanshu Jha
Use the new fast scan-out API in the PixelPump to render frames at a fixed frame rate in KVM mode. The refresh rate when running in KVM can be controlled by the virt_refresh_rate parameter. Change-Id: Ib3c78f174e3f8f4ca8a9b723c4e5d311a433b8aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2242 Reviewed-by: Rahul Thakur <rjthakur@google.com>
2017-03-07dev: Add support for single-pass scan out in the PixelPumpSudhanshu Jha
Add a helper function to scan out an entire frame in one time step. This requires the public PixelPump to be changed somewhat to separate timing updates from general PixelPump control. Instead of calling PixelPump::start(timings), timings now need to be updated using a separate call to PixelPump::updateTimings(timings) before calling PixelPump::start(). Display controllers that don't need accurate timing (e.g., in KVM mode), can use the new PixelPump::renderFrame() API to render an entire frame in one step. This call results in the same callbacks (e.g., calls to nextPixel()) as the timing calls, but they all happen in immediately. Unlike the timing counterpart, renderFrame() doesn't support buffer underruns and will panic if nextPixle() indicates an underrun. Change-Id: I76c84db04249b02d4207c5281d82aa693d0881be Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2241 Reviewed-by: Rahul Thakur <rjthakur@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-07arm, kmi: Clear interrupts in KMI devicesSudhanshu Jha
Added functionality to check and clear interrupts for KMI devices. This fixes a boot bug when using KVM and in-kernel GIC emulation. Change-Id: Ia3e91d07567b7faf3f82b0adfda4a165a502a339 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2225 Reviewed-by: Rahul Thakur <rjthakur@google.com>
2017-02-14arm, kvm: Automatically use the MuxingKvmGicAndreas Sandberg
Automatically use the MuxingKvmGic in the VExpress_GEM5_V1 platform. This removes the need to patch the host kernel or the platform configuration when using KVM on ARM. Change-Id: Ib1ed9b3b849b80c449ef1b62b83748f3f54ada26 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2017-02-14sim,kvm,arm: fix typosCurtis Dunham
Change-Id: Ifc65d42eebfd109c1c622c82c3c3b3e523819e85 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-11-09style: [patch 3/22] reduce include dependencies in some headersBrandon Potter
Used cppclean to help identify useless includes and removed them. This involved erroneously included headers, but also cases where forward declarations could have been used rather than a full include.
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-10-15arm, dev: pl011 console interactivityBjoern A. Zeeb
Improve PL011 console interactivity Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2016-10-07dev, arm: Make GenericTimer param handling more robustAndreas Sandberg
The generic timer needs a pointer to an ArmSystem to wire itself to the system register handler. This was previously specified as an instance of System that was later cast to ArmSystem. Make this more robust by specifying it as an ArmSystem in the Python interface and add a check to make sure that it is non-NULL. Change-Id: I989455e666f4ea324df28124edbbadfd094b0d02 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-09-22arm: disable GIC extensionsCurtis Dunham
Change-Id: If19b9c593b48ded1ea848f2d3710d4369ec8a221 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-09-06dev, arm: Add a customizable NoMali GPU modelAndreas Sandberg
Add a customizable NoMali GPU model and an example Mali T760 configuration. Unlike the normal NoMali model (NoMaliGpu), the NoMaliCustopmGpu model exposes all the important GPU ID registers to Python. This makes it possible to implement custom GPU configurations by without changing the underlying NoMali library. Change-Id: I4fdba05844c3589893aa1a4c11dc376ec33d4e9e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
2016-08-10arm, dev: Add support for listing DMA ports in new platformsAndreas Sandberg
When using a Ruby memory system, the Ruby configuration scripts expect to get a list of DMA ports to create the necessary DMA sequencers. Add support in the utility functions that wire up devices to append DMA ports to a list instead of connecting them to the IO bus. These functions are currently only used by the VExpress_GEM5_V1 platform. Change-Id: I46059e46b0f69e7be5f267e396811bd3caa3ed63 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
2016-08-10arm: Don't report the boot ROM as a memory in config tablesAndreas Sandberg
The boot ROM shouldn't be used as a memory by the kernel. Memories have a flag to indicate this which is set for some platforms. Update all platforms to consistently set this flag to indicate that the boot ROM shouldn't be reported as normal memory. Change-Id: I2bf0273e99d2a668e4e8d59f535c1910c745aa7b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com> --HG-- extra : amend_source : c2cbda38636ea37cbe9ae6977a06b923eab5ba56
2016-08-02arm: s/ctx_id/ctx/ the GICCurtis Dunham
Factored out of the larger banked register change. Change-Id: I947dbdb9c00b4678bea9d4f77b913b7014208690 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-02arm: bank GIC registers per CPUCurtis Dunham
Updated according to GICv2 documentation. Change-Id: I5d926d1abf665eecc43ff0f7d6e561e1ee1c390a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-06stats: Fixing regStats function for some SimObjectsDavid Guillen Fandos
Fixing an issue with regStats not calling the parent class method for most SimObjects in Gem5. This causes issues if one adds new stats in the base class (since they are never initialized properly!). Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-05-26dev, arm: Add a flag to enable/disable gem5 GIC extensionsAndreas Sandberg
Make it possible to disable gem5 gic extensions by setting the gem5_extensions param to False from Python. Change-Id: Icb255105925ef49891d69cc9fe5cc55578ca066d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Geoffrey Blake <geoffrey.blake@arm.com>
2016-05-26arm, dev: Remove superfluous loop increment in flash deviceAndreas Hansson
As identified by clang-3.8, there was a superfluous loop increment in the flash device which is now removed. Change-Id: If46a1c4f72d3d4c9f219124030894ca433c790af Reviewed-by: Rene De Jong <rene.dejong@arm.com>
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