summaryrefslogtreecommitdiff
path: root/src/dev/arm
AgeCommit message (Collapse)Author
2019-07-30dev-arm: Rewrite SMMUv3 CommandsGiacomo Travaglini
This patch is rewriting the SMMUv3::processCommand method for the following reasons: * Command names were not matching spec * Command encoding/opcode was wrong The patch is not adding any new command: there is still a subset of unimplemented commands; those are: * CMD_TLBI_EL3_ALL * CMD_TLBI_EL3_VA * CMD_TLBI_EL2_ALL * CMD_TLBI_EL2_VA * CMD_TLBI_EL2_VAA * CMD_TLBI_EL2_ASID which require StreamWorld support, and * CMD_ATC_INV * CMD_PRI_RESP * CMD_RESUME * CMD_STALL_TERM which require in sequence: ATS, PRI, Stall Model support Change-Id: Ia2dd47b5588738402d9584a00cfc88c94c253ad0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19668 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-25dev-arm: Fix SMMUv3 CMDQ wrappingGiacomo Travaglini
SMMU circular queues have a wrap bit which is used in order to distinguish between an empty queue and a full queue. According to SMMUv3 spec: Each index has a wrap flag, represented by the next higher bit adjacent to the index value contained in PROD and CONS. This bit must toggle each time the index wraps off the high end and back onto the low end of the buffer. It is the responsibility of the owner of each index, producer or consumer, to toggle this bit when the owner updates the index after wrapping. It is intended that software reads the register, increments or wraps the index (toggling wrap when required) and writes back both wrap and index fields at the same time. Change-Id: Idfeb397141f3627c2878caaeaa2625fadf671d2a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-by: Adrian Herrera <adrian.herrera@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19311 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-25dev-arm: Polish SMMUv3 CMDQ setupGiacomo Travaglini
The patch is aiming to be spec compliant when it comes to setup the SMMU command queue (while CR0.CMDQEN = 0), in the following ways: * Writes to CMDQ_CONS (read index) are allowed during initialization * Writes to CMDQ_BASE (cmdq pointer) are allowed during initialization According to spec, If they happen when the command queue is in fuction (CR0.CMDQEN = 1), behaviour is constrained unpredictable, with the following options 1) The write is ignored 2) The register takes the value and it is unpredictable whether it affects the SMMU command queue internal state. In the model/patch we go for option 1. Change-Id: I1c55bc571a8b3a1c0b0a525e429ab7b1480544ff Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19633 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-25dev-arm: Define enum masks for SMMU_CR0 registerGiacomo Travaglini
The configuration register is a vital register in the SMMU, and using enum masks will make the code more readable/understandable Change-Id: Ia117db56c457fe876ae38be391c386e502f34384 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19632 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-25dev-arm: TnSZ fields need to be cached in SMMUv3::ConfigCacheGiacomo Travaglini
Otherwise a hit after a table walk will result in a 0 value being read from the ConfigCache. Change-Id: I9813998acce44c93c5ce203f252ca80c10ba8f38 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-by: Adrian Herrera <adrian.herrera@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19631 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-25dev-arm: SMMUv3 Table walks using TnSZGiacomo Travaglini
TnSZ is needed when selecting the starting level of a table walk, since it directly affects the number of IA bits. This has been implemented by adding T0SZ and S2T0SZ to the translation context. T1SZ is not used at the moment since the current model doesn't support TTB1. Change-Id: I75663475c4dc01e5986cd93f8deafcdf7b1ece82 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19630 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-25dev-arm: Use override keyword for SMMUv3 PTOPSGiacomo Travaglini
Replacing the "virtual" keyword Change-Id: I0e7b4b683ea222827a67c3a81f0deea0e906c7e5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19629 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-25dev-arm: Add 16K granule support to SMMUv3 modelMichiel Van Tol
Added the necessary PageTableOps that match the 16K granule translation regime. Change-Id: I46ef07939cb4bdc8c0bbbeeeb6a50a9ab0d64de0 Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19628 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-19dev-arm: clang compatibility fix, added missing overridesMatteo Andreozzi
Change-Id: I5ee5ff788570178bb1d68878a26ac9e3ce636d8e Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19588 Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-16dev-arm: Fix SMMUv3 ContextDescriptor pointer shiftGiacomo Travaglini
The context descriptor pointer in the STE starts at the sixth LSB Change-Id: Ifa346b350785b788e9d1e093b662cb26433adfb8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Christo Smallwood <christo.smallwood@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19469 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-10dev-arm: A9SCU fixupTiago Muck
Shifting instead of expensive power. Change-Id: I164933257db125e18721c5b8bcaf9702030ebf40 Signed-off-by: Tiago Mück <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19408 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-01dev-arm: Use global import path for MemObjectGiacomo Travaglini
Change-Id: I66e0ca6df689ec6aeb831ef5545e8e5842bb0418 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19348 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-26dev-arm: Remove un-needed Q_CONS_PROD_MASK macroGiacomo Travaglini
Change-Id: I858d7eea088bbdd2dc12123e21e59991c896597f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19310 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-26dev-arm: drain implementation for SMMUv3Adrian Herrera
SMMUv3 is drained when (1) no SMMU translations are pending on any of its slave interfaces and (2) no commands are stored in the Command Queue waiting to be processed. Change-Id: I81cef5fd821fa5e509e130af02aece5239493df5 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19309 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-26dev-arm: pending SMMU transl update on constructor/destructorAdrian Herrera
Change-Id: I6f61651123aab129cfbe5a88aa6355cd21544a5e Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19308 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-17dev-arm: Reapply GICv3 changes that were lost during refactoringGiacomo Travaglini
The GICv3 code refactoring performed by: https://gem5-review.googlesource.com/c/public/gem5/+/16484 reverted the following patches https://gem5-review.googlesource.com/c/public/gem5/+/16544 https://gem5-review.googlesource.com/c/public/gem5/+/16545/3 This commit is reintroducing them Change-Id: I2c875c11570ed66ec9203449446faca3864c64d6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19229 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-06dev-arm: Implement a SMMUv3 modelStanislaw Czerniawski
This is an implementation of the SMMUv3 architecture. What can it do? - Single-stage and nested translation with 4k or 64k granule. 16k would be straightforward to add. - Large pages are supported. - Works with any gem5 device as long as it is issuing packets with a valid (Sub)StreamId What it can't do? - Fragment stage 1 page when the underlying stage 2 page is smaller. S1 page size > S2 page size is not supported - Invalidations take zero time. This wouldn't be hard to fix. - Checkpointing is not supported - Stall/resume for faulting transactions is not supported Additional contributors: - Michiel W. van Tol <Michiel.VanTol@arm.com> - Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: Ibc606fccd9199b2c1ba739c6335c846ffaa4d564 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19008 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-22dev-arm: Provide a GICv3 ITS ImplementationGiacomo Travaglini
This patch introduces the GICv3 ITS module, which is in charge of translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The patch is only GICv3 compliant, which means that there is no direct virtual LPI injection (this also means V* commands are unimplemented) Other missing features are: * No 2level ITS tables (only flat table supported) * Command errors: when there is an error in the ITS, it is IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible scenarios (see GICv3 TRM) and this implementation only supports one of these (which is, aborting the command and jumping to the next one). Furter patches could make it possible to select different reactions * Invalidation commands (INV, INVALL) are only doing the memory table walks, assuming the current Gicv3Redistributor is not caching any configuration table entry. Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Store a PhysProxy port in Gicv3RedistGiacomo Travaglini
This spares us from retrieving the TC pointer every time we want to write/read to memory (LPIs) Change-Id: Iad76b5e69188fa0ac5c6777a3b2664b0fc66b12f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18600 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Add named variable for GICD_TYPER.IDBitsGiacomo Travaglini
This could be used by other GICv3 components to query the maximum number of implemented interrupt identifiers Change-Id: I132e50de331aea22523260bcefba7e961b53eccd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18599 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Read correct version of ICC_BPR registerGiacomo Travaglini
Some methods like groupPriorityMask check for the value of binary point registers. Those registers have a minimum value. Writing to those register is taking this into account, but the problem with the minimum value arises when the value is checked before sw is writing to them. In this case the minimum value won't be considered if the read is directly forwarded to the ISA class. Change-Id: Id432a37f1634b02bc478d65c52ffb88323d4bb77 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18598 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Get a Gicv3Redistributor ptr from phys addressGiacomo Travaglini
The patch is adding the following method to Gicv3: * Gicv3::getRedistributorByAddr This will be needed by the ITS when trying to select the target redistributor after decoding the collection table entry (RDBase). Change-Id: I40e2c155f2fdc8ca6d3c20ff7a27702e02499f20 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18597 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Add several LPI methods in Gicv3RedistributorGiacomo Travaglini
Refactoring the existing in code in smaller methods will be crucial when adding the ITS module, which is a client for the redistributor class and which will require it to take different actions depending on the command it receives from software. List of methods: * read/writeEntryLPI Reading/Writing a byte from the LPI pending table * isPendingLPI Checks if the pINTID LPI is set. Knowing if an LPI is set is needed by the MOVI command, which is transfering the pending state from one redistributor to the other only if the LPI is pending. Change-Id: If14b1c28ff7f2aa20b12dcd822bf6a490cbe0270 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18596 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Take LPIs into account when interacting with CPUIF regsGiacomo Travaglini
Previous code was not handling LPIs when it came to activation/deactivation of interrupts. Change-Id: Ie38f83c66afdc42132679d7e2e5823990f1710d0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18595 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Fix GICv3 LPIs priority valueGiacomo Travaglini
Priority bits in the LPI configuration table entry are only the MSBits ([7:2]) and need to be shifted in order to get the real LPI priority value. Change-Id: Id04dd4fa9113a32712c73a7094df498de3c0d2b5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18594 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Disable LPI Configuration Table cachingGiacomo Travaglini
This is done since caching is not done correctly, and we don't care for now about performance degradations since the redistributor is using PhysProxy ports. Caching will make sense once the magical accesses will be replaced by real atomic/timing transactions. Change-Id: Iafe2a7843210111efc82c265bd0d5ec3cd9abb5a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18593 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Check EnableLPIs before checking for pending LPIsGiacomo Travaglini
Before reading the tables, GICR_PENDBASER and GICR_PROPBASER need to be properly set, and those will have a consistent value only once sw enables LPIs. Change-Id: Ifb87944a491045e7a13ce7a280c555cb0c1e47f4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18592 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: GICv3 LPI tables are using physical addressesGiacomo Travaglini
Change-Id: I439112f318720ae74c43a374fd3a524c607b3a23 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18591 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Fix GICv3 LPI loopGiacomo Travaglini
Loop was mistakenly increasing the upper bound of the iteration rather than the index variable itself. Change-Id: I0a5a7bc189bc0954a8a6d9581032c2ed902030da Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18590 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-02dev-arm: Fix Bitwise operation in GICv3Giacomo Travaglini
GICv3 LPI code is wrongly using the xor operator (^) in order to evaluate powers of two. Change-Id: Ib1131fd5940d334967a3741f8fd15d86625be356 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18589 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Move GICv3 (Re)Ditributor address in Realview.pyGiacomo Travaglini
Base addresses for GICv3's Distributor and Redistributors are implementation defined: they depend on the platform rather than the model. This patch is then moving dist_addr and redist_addr initialization in Realview.py Change-Id: I1246df500262f4d3d5a38e62d0240945f90941ee Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18393 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Limit number of max PE in GICv3 to 128Giacomo Travaglini
This is needed since there is a problem in the memory layout of VExpress_GEM5_V2 as it is: having 256KB pages is creating overlapping regions when reserving space for 256 PEs. GICv3 redistributors: 0x2c010000 - 0x30010000 PCI regions: 0x30000000 - 0x40000000 We fix this by cutting down the number of supported PEs to 128 Change-Id: I6e87f66a6150a441ccba298662b4548a4972dc40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18392 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Add GICv4 extension switch in GICv3Giacomo Travaglini
This is currently used only for determining which is the correct size of redistributors in memory (256KB in GICv4 and 128KB in GICv3) Change-Id: I2c07005e97167fde03548313c9927176788f31dd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18391 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Check for maximum number of supported PE in GICv3Giacomo Travaglini
This is currently set to 256 Change-Id: If7bb2847c22f29bfa0cb4ebf4a7984ee43ab4e29 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18390 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27dev-arm: Rename GIC maintenance interrupt from ppint to maint_intGiacomo Travaglini
ppint is a generic name which only reflects Arm recommendation of assigning the maintanance interrupt to a PPI (numbered 25) Change-Id: Ic5abb6ed50817ad2d165b5df46dd989eb195a9db Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17628 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27dev-arm: Fix GICv3 overflow for INTID > 256Giacomo Travaglini
SPIs can get to a maximum number of 1023, so that an uint8_t is not capable of representing all of them. Change-Id: I7a2c43b41ac93eabdfcf8311681240416b954177 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17631 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)Giacomo Travaglini
For SGIs and PPIs: * When ARE is 1 (only value supported in gem5) for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case. Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-26dev-arm: Set/Unset dma coherent mode from pythonGiacomo Travaglini
With this patch it will be possible to automatically enable/disable the dma-coherent property for the GenericArmPciHost autogenerated DTB. This has been done by adding the _dma_coherent param. Change-Id: I1759fced74e42410462637ca77997a351314a90a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16748 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-14dev-arm: cleanup of gicv3 CPU interface code and fixesJairo Balart
Change-Id: I4643140f60da4dc9179b5bfed1e3ddd7c2f23091 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16484 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-12dev-arm: cleanup of gicv3 codeJairo Balart
Change-Id: I9aba90022f6408838c4ab87c6b90bba438752e53 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16222 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-01dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on readsGiacomo Travaglini
Reading ICV_PMR_EL1 should return the value the VMCR_EL2.VPMR bits which are aliased to the register. Change-Id: Id3e6dfb196f3726edaa3eddb244765598ed62334 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16545 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-01dev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping on readsGiacomo Travaglini
Reading ICV_IGRPEN<n>_EL1 should return the value of VMCR_EL2.VENG0 and VMCR_EL2.VENG1 bits. Change-Id: Ia5d748cf60ba074cccf4c127ac479c5cb881773d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16544 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-18dev-arm: LPI support for GICv3. This doesn't include an ITS model.Jairo Balart
Change-Id: Ia2c02cca4f95672d6361fba16201a56e2047ddb7 Reviewed-on: https://gem5-review.googlesource.com/c/16142 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files. Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-07configs, arch-arm: Using AddrRange for Realview mem_regionsGiacomo Travaglini
Physical memory ranges are now saved in Realview objects as pairs of addresses (start address and size). This patch is substituting them with a single AddrRange object. Change-Id: I02d25d557c5c54d062f0dccef8ede45744d0ce6b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16206 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-01dev, arm: Removed contextId variableAnouk Van Laer
The contextId variable is only used by the debug flag and will prevent a more optimised binary (i.e. fast) from compiling. Change-Id: I6cefb5bc06d0d4b415df62f1278db53ba309fb87 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16042 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-24dev-arm: fix --generate-dtb for ARMCiro Santilli
Was failing with: NameError: global name 'FdtNode' is not defined The problem was introduced at: 75831ce5b7880b67c1aa2e0871ce16d5c01cadc7 Change-Id: I7e2ce0e5311e7814229945b9f4e7318a8652dc1f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15875 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.Gabe Black
Other dev code was already switched over. This code was written before the switch over (or unaware of it), and checked in after. Change-Id: Ibb9e9e4300d01cc46e4dae668274debc2a4989ba Reviewed-on: https://gem5-review.googlesource.com/c/15755 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-07 03:50:05 +0000