gem5 - gem5

Age	Commit message (Expand)	Author
2018-04-27	sim,cpu,mem,arch: Introduced MasterInfo data structure	Giacomo Travaglini
2017-07-10	dev: Fix OnIdle test in DmaReadFifo	Rohit Kurup
2017-06-20	dev: Replace EventWrapper use with EventFunctionWrapper	Sean Wilson
2017-03-07	dev, kvm: Add a fast KVM-aware mode in DmaReadFifo	Sudhanshu Jha
2015-12-31	mem: Make cache terminology easier to understand	Andreas Hansson
2015-08-07	dev: Add a simple DMA engine that can be used by devices	Andreas Sandberg
2015-07-07	sim: Refactor and simplify the drain API	Andreas Sandberg
2015-07-07	sim: Decouple draining from the SimObject hierarchy	Andreas Sandberg
2015-07-07	sim: Make the drain state a global typed enum	Andreas Sandberg
2015-05-05	mem: Snoop into caches on uncacheable accesses	Andreas Hansson
2015-03-02	mem: Split port retry for all different packet classes	Andreas Hansson
2014-12-23	arm: Add stats to table walker	Curtis Dunham
2014-01-24	mem: per-thread cache occupancy and per-block ages	Dam Sunwoo
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-02-15	sim: Add a system-global option to bypass caches	Andreas Sandberg
2013-01-07	dev: Fix infinite recursion in DMA devices	Andreas Sandberg
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-10-23	dev: Remove zero-time loop in DMA timing send	Andreas Hansson
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-08-22	DMA: Refactor the DMA device and align timing and atomic	Andreas Hansson
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-07-27	dma: remove unused variable	Anthony Gutierrez
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-05-23	DMA: Split the DMA device and IO device into seperate files	Andreas Hansson