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path: root/src/dev/dma_device.cc
AgeCommit message (Expand)Author
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
2017-07-10dev: Fix OnIdle test in DmaReadFifoRohit Kurup
2017-06-20dev: Replace EventWrapper use with EventFunctionWrapperSean Wilson
2017-03-07dev, kvm: Add a fast KVM-aware mode in DmaReadFifoSudhanshu Jha
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
2015-08-07dev: Add a simple DMA engine that can be used by devicesAndreas Sandberg
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-05-05mem: Snoop into caches on uncacheable accessesAndreas Hansson
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2014-12-23arm: Add stats to table walkerCurtis Dunham
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-01-07dev: Fix infinite recursion in DMA devicesAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-10-23dev: Remove zero-time loop in DMA timing sendAndreas Hansson
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-08-22DMA: Refactor the DMA device and align timing and atomicAndreas Hansson
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-07-27dma: remove unused variableAnthony Gutierrez
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-05-23DMA: Split the DMA device and IO device into seperate filesAndreas Hansson