Age | Commit message (Collapse) | Author |
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Moved DescCache template functions from .hh to .cc file.
Also fixed lots of line-wrapping problems, and some irregular indentation.
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For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
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starts/ends as well as after read/write dmas
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postedInterrupts statistics.
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moderation not always delay if no interrupts have been posted for the ITR value.
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of those statistics to the e1000 model.
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creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
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now encoded in cmd field.
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src/dev/i8254xGBe.cc:
src/dev/i8254xGBe.hh:
couple more bug fixes
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add seperate response buffers and request queue sizes in bus bridge
add delay to respond to a nack in the bus bridge
src/dev/i8254xGBe.cc:
src/dev/ide_ctrl.cc:
src/dev/ns_gige.cc:
src/dev/pcidev.hh:
src/dev/sinic.cc:
add backoff delay parameters
src/dev/io_device.cc:
src/dev/io_device.hh:
add a backoff algorithm when nacks are received.
src/mem/bridge.cc:
src/mem/bridge.hh:
add seperate response buffers and request queue sizes
add a new parameters to specify how long before a nack in ready to go after a packet that needs to be nacked is received
src/mem/cache/cache_impl.hh:
assert on the
src/mem/tport.cc:
add a friendly assert to make sure the packet was inserted into the list
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src/dev/i8254xGBe.cc:
src/dev/i8254xGBe.hh:
src/dev/i8254xGBe_defs.hh:
finish coding the Intel Gb NIC device
src/dev/io_device.hh:
we really don't want to be able to pass a null buffer to dma read, at least not the way we have things setup now... it won't work at all
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support enough functionality make the driver think
the device is there, and in good working order.
src/dev/SConscript:
add intel gbe to the dev SCons file
src/dev/i8254xGBe.cc:
src/dev/i8254xGBe.hh:
src/dev/i8254xGBe_defs.hh:
use new manner of registers and implement all device registers that are touched through boot and ifup
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into zeep.pool:/z/saidi/work/m5.newmem.head
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src/SConscript:
add intel nic to sconscript
src/dev/pcidev.cc:
fix bug with subsystemid value
src/python/m5/objects/Ethernet.py:
add intel nic to ethernet.py
src/python/m5/objects/Ide.py:
src/python/m5/objects/Pci.py:
Move config_latency into pci where it belogs
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