gem5 - gem5

Age	Commit message (Expand)	Author
2011-08-19	IDE: Fix issues with new PIIX kernel driver and our model.	Ali Saidi
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-04	IDE: Support x86, Alpha, and ARM use of the IDE controller.	Ali Saidi
2010-11-22	IDE,X86: Fix IDE controller BAR configuration for x86.	Gabe Black
2010-11-15	ARM: Add support for a dumb IDE controller	Ali Saidi
2009-11-18	m5: removed master and slave deletions.	Brad Beckmann
2009-08-02	IDE: Configure the IDE control to reflect the initial value of the command re...	Gabe Black
2008-12-14	The ide_ctrl serialize and unserialize were broken.	Author Name
2008-12-09	IDE: Fix serialization for the IDE controller.	Richard Strong
2008-12-07	Devices: Clean up the IDE controller.	Gabe Black
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-06-30	Can only call makeAtomicResponse() once...	Steve Reinhardt
2007-06-30	Get rid of Packet result field. Error responses are	Steve Reinhardt
2007-05-09	add a backoff algorithm when nacks are received by devices	Ali Saidi
2006-10-20	Use PacketPtr everywhere	Nathan Binkert
2006-10-19	refactor code for the packet, get rid of packet_impl.hh	Nathan Binkert
2006-10-08	post checkpoint restoration the bus ranges need to be re-initialized for ALL ...	Lisa Hsu
2006-07-27	Need config read/write latency.	Kevin Lim
2006-07-06	Add default responder to bus	Ali Saidi
2006-05-31	Updated Authors from bk prs info	Ali Saidi
2006-05-30	Minor further cleanup & commenting of Packet class.	Steve Reinhardt
2006-05-26	Significant rework of Packet class interface:	Steve Reinhardt
2006-05-22	New directory structure:	Steve Reinhardt