gem5 - gem5

Age	Commit message (Expand)	Author
2019-04-28	mem: Minimize the use of MemObject.	Gabe Black
2019-03-19	arch, cpu, dev, gpu, mem, sim, python: start using getPort.	Gabe Black
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2015-11-06	mem: Use the packet delays and do not just zero them out	Andreas Hansson
2015-07-07	sim: Decouple draining from the SimObject hierarchy	Andreas Sandberg
2015-07-07	sim: Make the drain state a global typed enum	Andreas Sandberg
2015-02-11	mem: Clarification of packet crossbar timings	Marco Balboni
2014-12-08	dev: Add response sanity checks in PioPort	Andreas Sandberg
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2013-07-11	dev: make BasicPioDevice take size in constructor	Steve Reinhardt
2013-02-19	mem: Enforce strict use of busFirst- and busLastWordTime	Andreas Hansson
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-05-23	DMA: Split the DMA device and IO device into seperate files	Andreas Hansson
2012-05-23	MEM: Add a snooping DMA port subclass for table walker	Andreas Hansson
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-16	Merge yet again with the main repository.	Gabe Black
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	MEM: Simplify ports by removing EventManager	Andreas Hansson
2012-01-10	DPRINTF: Improve some dprintf messages.	Nilay Vaish
2012-01-07	Another merge with the main repository.	Gabe Black
2012-01-07	Merge with the main repository again.	Gabe Black
2012-01-07	Merge with main repository.	Gabe Black
2011-12-15	IO: Fix bug in DMA Device where receiving a snoop on DMA port would cause a p...	Ali Saidi
2011-12-01	Device: Make changes necessary to support a coherent page walker cache.	Mitchell Hayenga
2011-10-20	dev: clean up PioDevice and DmaDevive getPort() methods.	Steve Reinhardt
2011-10-08	Ports: Print the port name when a port is used but not attached to anything.	Gabe Black
2011-10-04	SE/FS: Put platform pointers in fewer objects.	Gabe Black
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-03-17	Mem: Fix issue with dirty block being lost when entire block transferred to n...	Ali Saidi
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-11-08	Bus: Have the I/O devices that return address ranges print them out.	Ali Saidi
2010-08-23	Devices: Allow a device to specify that a request is uncachable.	Gene Wu
2010-06-02	DMA: Make DmaPort generic enough to be used other places	Ali Saidi
2008-10-09	eventq: convert all usage of events to use the new API.	Nathan Binkert
2008-08-26	Device: Fix bug in DmaPort::recvRetry. The interface attempts to send the sam...	Clint Smullen
2008-08-13	Add the ability for a DMA to tack on an extra delay after the DMA is actually...	Ali Saidi
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-07-14	Merge of DPRINTF fixes from head.	Steve Reinhardt