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path: root/src/dev/pcidev.cc
AgeCommit message (Expand)Author
2014-12-02mem: Remove redundant Packet::allocate callsAndreas Hansson
2014-10-16dev: refactor pci config space for sysfs scanningGeoffrey Blake
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-03dev: seperate legacy io offsets from PCI offsetAli Saidi
2013-10-31dev: Add support for MSI-X and Capability Lists for ARM and PCI devicesGeoffrey Blake
2013-07-11dev: consistently end device classes in 'Device'Steve Reinhardt
2013-02-19mem: Enforce strict use of busFirst- and busLastWordTimeAndreas Hansson
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-28Merge with the main repo.Gabe Black
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2011-10-04SE/FS: Put platform pointers in fewer objects.Gabe Black
2011-08-19ARM: Add VExpress_E support with PCIe to gem5Ali Saidi
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2010-11-15ARM: Add support for a dumb IDE controllerAli Saidi
2010-09-10style: fix sorting of includes and whitespace in some filesNathan Binkert
2009-02-01Devices: Add support for legacy fixed IO locations in BARs.Gabe Black
2008-12-15PCI: Add some missing breaks to a couple case statements.Gabe Black
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...Ali Saidi
2007-08-16PCI: Move PCI Configuration data into devices now that we can inherit paramet...Ali Saidi
2007-08-16Devices: Make EtherInts connect in the same way memory ports currently do.Ali Saidi
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-06-30Can only call makeAtomicResponse() once...Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
2006-11-10fix endian issues with condition codesAli Saidi
2006-11-06Moved the tsunami devices into the dev/alpha directory. Other devices "generi...Gabe Black
2006-10-20Use PacketPtr everywhereNathan Binkert
2006-10-19refactor code for the packet, get rid of packet_impl.hhNathan Binkert
2006-10-08post checkpoint restoration the bus ranges need to be re-initialized for ALL ...Lisa Hsu
2006-09-18add boiler plate intel nic codeAli Saidi
2006-08-30Move more common functionality into SimpleTimingPort,Steve Reinhardt
2006-08-30Minor include file & formatting cleanup.Steve Reinhardt
2006-08-28Clean up BAR setting code.Steve Reinhardt
2006-08-28Get rid of unneeded union.Steve Reinhardt
2006-08-28Get rid of unused BARAddrs[] in PciConfigData object.Steve Reinhardt
2006-08-28Cleanup: formatting, comments, DPRINTFs.Steve Reinhardt
2006-07-12memory mode information now contained in system objectAli Saidi
2006-07-06Add default responder to busAli Saidi
2006-05-31Updated Authors from bk prs infoAli Saidi
2006-05-22New directory structure:Steve Reinhardt
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