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x86
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Pc.py
Age
Commit message (
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Author
2015-12-05
dev: Rewrite PCI host functionality
Andreas Sandberg
2014-11-21
x86: pc: Put a stub IO device at port 0xed which the kernel can use for delays.
Gabe Black
2014-07-18
x86: make PioBus return BadAddress errors
Binh Pham
2013-11-25
sim: simulate with multiple threads and event queues
Steve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2012-11-02
sim: Include object header files in SWIG interfaces
Andreas Sandberg
2012-04-05
Config: corrects the way Ruby attaches to the DMA ports
Nilay Vaish
2012-02-13
MEM: Introduce the master/slave port roles in the Python classes
Andreas Hansson
2010-08-17
bus: clean up default responder code.
Steve Reinhardt
2009-02-01
X86: Plug in an IDE controller.
Gabe Black
2009-01-25
X86: Add a device to back the non-existant floppy drive controller.
Gabe Black
2009-01-25
X86: Add fake devices for non-existant serial ports.
Gabe Black
2008-10-11
X86: Rename the PC device to Pc.
Gabe Black
