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path: root/src/dev/x86/Pc.py
AgeCommit message (Expand)Author
2015-12-05dev: Rewrite PCI host functionalityAndreas Sandberg
2014-11-21x86: pc: Put a stub IO device at port 0xed which the kernel can use for delays.Gabe Black
2014-07-18x86: make PioBus return BadAddress errorsBinh Pham
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-04-05Config: corrects the way Ruby attaches to the DMA portsNilay Vaish
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2010-08-17bus: clean up default responder code.Steve Reinhardt
2009-02-01X86: Plug in an IDE controller.Gabe Black
2009-01-25X86: Add a device to back the non-existant floppy drive controller.Gabe Black
2009-01-25X86: Add fake devices for non-existant serial ports.Gabe Black
2008-10-11X86: Rename the PC device to Pc.Gabe Black