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path: root/src/dev/x86/SouthBridge.py
AgeCommit message (Expand)Author
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-08-21Device: Remove overloaded pio_latency parameterAndreas Hansson
2012-04-05Config: corrects the way Ruby attaches to the DMA portsNilay Vaish
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
2011-05-23config: revamp x86 config to avoid appending to SimObjectVectorsSteve Reinhardt
2009-08-02X86: Set up the IDE device correctly, ie. with and using legacy ports.Gabe Black
2009-02-01X86: Configure the first PCI interrupt.Gabe Black
2009-02-01X86: Hook up the IDE controller interrupt line.Gabe Black
2009-02-01X86: Plug in an IDE controller.Gabe Black
2009-01-31X86: Add a keyboard controller device.Gabe Black
2009-01-31X86: Rework interrupt pins to allow one to many connections.Gabe Black
2009-01-25X86: Add a dummy minimal DMA controller that doesn't do anything.Gabe Black
2008-10-12X86: Make APICs communicate through the memory system.Gabe Black
2008-10-11X86: Create an IO APIC device.Gabe Black
2008-10-11X86: Bring the South Bridge device into dev/x86 and get rid of south_bridge d...Gabe Black