gem5 - gem5

Age	Commit message (Expand)	Author
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-08-21	Device: Remove overloaded pio_latency parameter	Andreas Hansson
2012-04-05	Config: corrects the way Ruby attaches to the DMA ports	Nilay Vaish
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-17	MEM: Removing the default port peer from Python ports	Andreas Hansson
2011-05-23	config: revamp x86 config to avoid appending to SimObjectVectors	Steve Reinhardt
2009-08-02	X86: Set up the IDE device correctly, ie. with and using legacy ports.	Gabe Black
2009-02-01	X86: Configure the first PCI interrupt.	Gabe Black
2009-02-01	X86: Hook up the IDE controller interrupt line.	Gabe Black
2009-02-01	X86: Plug in an IDE controller.	Gabe Black
2009-01-31	X86: Add a keyboard controller device.	Gabe Black
2009-01-31	X86: Rework interrupt pins to allow one to many connections.	Gabe Black
2009-01-25	X86: Add a dummy minimal DMA controller that doesn't do anything.	Gabe Black
2008-10-12	X86: Make APICs communicate through the memory system.	Gabe Black
2008-10-11	X86: Create an IO APIC device.	Gabe Black
2008-10-11	X86: Bring the South Bridge device into dev/x86 and get rid of south_bridge d...	Gabe Black