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2019-09-21x86: Templatize the IntMasterPort.Gabe Black
This makes the IntMasterPort usable with any class, making it possible to avoid inheriting from IntDevice. It also makes IntMasterPort inherit directly from QueuedMasterPort, skipping over MessageMasterPort. Change-Id: I9d218556c838ea567ced5f6fa4d57a3ec9d28d31 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20821 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-09-21x86: Templatize IntSlavePort.Gabe Black
This makes the device IntSlavePort calls back into based on a template parameter so that IntDevice doesn't have to be in the inheritance hierarchy to use it. It also makes IntSlavePort inherit from SimpleTimingPort directly, skipping over MessageSlavePort. Change-Id: Ic3213edc9c3ed5e506ee1e9f5e082cd47d7c7998 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20820 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-09-20dev, x86: Delete the now unused X86 specific interrupt pins/lines.Gabe Black
Change-Id: I3915f0ad673119b551dcc4c5cedec180a9b88735 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20702 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-20dev, x86: Convert x86 devices to the generic int pins.Gabe Black
Change-Id: I4551ad00cf205c31555c90b53e87bc206a8d8729 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20701 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19dev: Terminal output's dump name conflictsAndrea Mondelli
The recently Terminal dump options name introduced in patch 1c72e90 conflict with MacOS stdio.h header. From stdio.h: #define stdin __stdinp #define stdout __stdoutp #define stderr __stderrp To remove this conflict, the TerminalDump options are renamed. Change-Id: I1b60fa1031328fc32d6a58bf7889b6e479d95219 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20959 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19dev-arm: Conditionally enable HDLcd when doing DTB autogenGiacomo Travaglini
This is a preparation change for a real DTB autogen implementation Change-Id: Ia0c1c5e65ea96036e55455eb4222cec12944d33a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20331 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19dev-arm: Add HDLcd DTB autogenerationGiacomo Travaglini
A Display has been defined. Its sole purpose is to generate the device tree node to be referenced by the HDLcd device. The encoder parameters are based on the existing node defined in: system/arm/dt/armv8.dts Change-Id: I6cdeb0437dce207dbd0f2c65c16b224245eb74e1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20330 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-16dev-arm: Allow IOMMU binding to HDLcdGiacomo Travaglini
Change-Id: I894080e7bd76e7efedef141c937e1561c0c0527c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20841 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-13dev-arm: Store the IOMMU reference from within the SMMU::connectGiacomo Travaglini
Change-Id: I35718a71dc040ee4acad9eee2a07076ebb571304 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20840 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-13dev: Enable DTB IOMMU binding with a DMA objectGiacomo Travaglini
This happens by storing a iommu reference in the dma device, and by calling the addIommuProperty method once doing dtb autogeneration for the device Change-Id: Ibd585addac686a9eeaba6959f459d81901087549 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20839 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-12dev: Generalize the x86 int source/sink pins.Gabe Black
Sink pins are now templated based on the underlying device types, and the pins themselves are based on the new, generalized Port mechanism. Change-Id: I09c678c56f6eb6b4a167c12f221ae0241fe99c2d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20700 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-09dev-arm: Reset HPPI when clearing an LPIGiacomo Travaglini
Change-Id: I2a69e6cef69aa48d7c265d59915b859e5eac2bcc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20638 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Add resetHppi method in the GICv3 cpu interfaceGiacomo Travaglini
The method is used for resetting the highest priority pending interrupt interrupt from the cpu interface if it matches the intid passed as an argument. Change-Id: I9fbc4cb3e05a1cc32f853b6afab5c2bc99369435 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20637 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Cleanup GICv3 initializationGiacomo Travaglini
This patch is removing the unnecessary initState() / reset() methods from GICv3 classes, since we can initialize everything at construction/init time Change-Id: Ia70edcc4ca4f11878fac0024342e4f2cd81883a0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20636 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Initialize GICD_TYPER once at construction timeGiacomo Travaglini
Change-Id: Ib4dfdf7005709c22b4ba95099b1192f6edd6ff06 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20635 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Writes to IGRPEN1_EL3 triggering updateGiacomo Travaglini
Change-Id: I56804eb1bfc8913bd0d3cab05865a382bf270bc1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20634 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Fix GICv3 ITS cmdq wrappingGiacomo Travaglini
Change-Id: I979e8d1378d5b5d2647158798479cf4238f2c349 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20633 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1Giacomo Travaglini
Previous mapping was wrong because it was checking which security bits it was accessing by using the inSecureState() function, whereas it should have used the isSecureBelowEL3(). This patch is not making the sostitution since it is optimizing the mapping furthermore by avoiding updating both IGRPEN1_EL1 and IGRPEN1_EL3 on writes. The IGRPEN1_EL1 register is used as a storage, and any reads/writes to IGRPEN1_EL3 is routed to that register. Change-Id: Id318ec44e19d4f844e4e3410d74d0c4f89810811 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20632 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev-arm: Implement message-based SPIsGiacomo Travaglini
Change-Id: I35e79dfd572c3e0d9cadc8e0aab01befd6004ece Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20631 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-09dev: Scrub out some lingering uses of MemObject.Gabe Black
MemObject doesn't do anything any more, and is basically just an alias for ClockedObject. Change-Id: Ic0e1658609e4e1d7f4b829fbc421f222e4869dee Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20719 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-07dev-arm: Add GICD_SGIR registerGiacomo Travaglini
The Distributor Software Generated Interrupt Register is implemented only if affinity routing is disabled. Since this configuration is currently not supported in gem5, it has to be treated as RES0. Change-Id: I9ffcb31b26fc17547f74a4f1d43ce72c59786fa8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20630 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-06dev: Enable Terminal output's dump to stdoutGiacomo Travaglini
While the default option is to dump the Terminal content in a file (e.g. m5out/system.terminal), with this patch it will be possible to choose to dump it to standard output. Change-Id: If51c2fd671fa3eb0867a855b5f7d3b0df9cad025 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20639 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-06dev-arm: State update when setting MISCREG_ICC_IGRPENx registerGiacomo Travaglini
This is because by enabling ainterrupt group at the cpu interface, we need to check if a previously pending interrupt needs to be forwarded to the PE. We are doing the same when globally enabling irqs in the distributor (GICD_CTLR). Change-Id: I80aeb87b2a58a108de899006d5a2f12eadbe6c2e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20629 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ic08ac1e7f3ebef408a83aa068ce15e9dfe2aa3cd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20628 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ide93464f62288fbe8f409f718487a15512c01295 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20627 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Add read/writeBanked helpers to GICv3Giacomo Travaglini
These will be used by AA64 security banked registers in GICv3. Change-Id: Ia980c4f5c14187ab9c18da1d1d596562644111ae Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20624 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev: Fix segmentation fault in VirtIOBlockChun-Chen TK Hsu
GEM5 got a segmentation fault when the size is large in VirtIOBlock::write. This change uses a vector to avoid this segmentation fault. Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Change-Id: I26272686a6e7e39cdf2389657ecd38ce90261144 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20679 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Rewrite ICC_BPR0/ICC_BPR1 handlingGiacomo Travaglini
The patch is fixing BPR reads in AA32, by removing the line Gicv3::GroupId group = misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S; Where a read to ICC_BPR0 will return a G1S group. The patch is also fixing Security banking accesses. Change-Id: I28f1d1244c44d4b8b202d3141f8380943c7c1c86 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20620 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Add GICv3 unimplemented Hyp Active Priorities Group regsGiacomo Travaglini
ICH_APxR1, ICH_APxR2, ICH_APxR3 are implemented only if supporting more than 6 bits of priority. Since this is not the case, they are currently unimplemented. According to spec, unimplemented registers are RAZ/WI. Change-Id: Ifd7f7a3d42b4575c2f7aff3b95d5a47ac1e61842 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20619 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Allow 32-bit access to GITS_TYPERGiacomo Travaglini
Change-Id: I9d19174b38ba70f82050102f955ccc162965d1fb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20618 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Cpu interface groupEnabled check for global enableGiacomo Travaglini
Gicv3CPUInterface::groupEnabled should check for global enable flags at distributor level: - Gicv3Distributor.EnableGrp0 - Gicv3Distributor.EnableGrp1S - Gicv3Distributor.EnableGrp1NS Change-Id: I1c855b0e4c2bc8f1cd0a8f086b9450f516177b08 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20617 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Check if INTID group is enabled when reading HPPIRxGiacomo Travaglini
If it is not enabled, it should return INTID_SPOURIOUS Change-Id: I4dfa8b9fcea874b4d281cd154dd38752b05e1d59 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20616 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Writing GICD_CTLR should trigger an updateGiacomo Travaglini
This is the case where an interrupt is pending, but the distributor is masking it. As soon as the group gets enabled, the interrupt should be forwarded to the PE. Change-Id: Ie428780bde7e4726688adf78dfcc4d43d1b45261 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20615 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Rewrite GICv3 updateGiacomo Travaglini
The GICv3 update methods are method which are invoked anytime the model needs to evaluate a change in its state, which most of the time means managing the state of an interrupt (forwarding it to a PE, deasserting it, etc). The way it is currently done is a little bit obscure and doesn't handle correctly IRQ prioritization. Example: An IRQ which is handled by the redistributor (PPI or LPI) was not competing with any pending interrupts coming from the distributor (SPIs) once raised by a peripheral. Also the way the pending state of an interrupt was removed at the cpu interface level wasn't happening in place where this was actually happening (E.g. when activating it), but happened with a weird fullUpdate semantic, where if there was a pending interrupt in a cpu interface, all cpu interfaces had their pending interrupt (if any) been disabled. With this patch, state update always starts at the distributor, and it goes down until the cpu interface where a Gicv3CPUInterface::update method selects the winning interrupt coming from distributor/redistributor to be forwarded to the PE. Change-Id: I1c517cbc4bf107cc2d7ae7beb2692e3cf5187a40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20614 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Fix GICv3 IGRPMOD writesGiacomo Travaglini
Writes to IGRPMOD were not right shifting the value, which resulted in interrupts having a IGRPMOD value > 1, whereas the only allowed values are 0 and 1. Change-Id: Id491bd1b184d6e5abeeea25ea272eeb91792ccf7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20613 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Fix SGI generationGiacomo Travaglini
The patch is fixing the following aspects of SGIs * The conditons over which an SGI can be forwarded to a PE * SGIs in AArch32 (see below) It is in fact refactoring SGI generation under a common method in the cpu interface. It is abandoning the implicit fallthrough mechanism not only for cosmetic reasons, but also because checking "misc_reg ==" was only working if the register was an AArch64 one (e.g. MISCREG_ICC_SGI0R_EL1) and not the AArch32 counterpart (MISCREG_SGI0R). Change-Id: I6fedfb80388666f4f1d20f6abef378a9f093aa83 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20610 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: Gicv3 ITS device tree autogenAdrian Herrera
This patch adds device tree automatic generation for Gicv3 ITS. Change-Id: Ic01500ffa691b331f527c5c2c785ff715660b0c2 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20609 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06dev-arm: modify GICv3 ITS default addrAdrian Herrera
The current default base address for GICv3 ITS stated in RealView is 0x2c120000. The redistributors base address is 0x2c010000; each instantiated core has an associated redistributor with memory region size 0x40000 (with GICv4 extension, enabled by default). With 8 cores, the redistributor range spans to 0x2c210000, creating a conflict with the ITS address space. This patch changes the ITS base address to 0x2e010000 which guarantees no overlapping with the redistributor. Change-Id: I7dc1af9e69ac037f85ae96f0985554f1fb8372a0 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20608 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-05dev-arm: Improper translation slot release in SMMUv3Giacomo Travaglini
The SMMUv3SlaveInterface is using the xlateSlotsRemaining to model a limit on the number of translation requests it can receive from the master device. Patch https://gem5-review.googlesource.com/c/public/gem5/+/19308/2 moved the resource acquire/release inside the SMMUTranslationProcess constructor/destructor, for the sake of having a unique place for calling the signalDrainDone. While this is convenient, it breaks the original implementation, which was freeing resources AFTER a translation has completed, but BEFORE the final memory access (with the translated PA) is performed. In other words the xlateSlotsRemaining is only modelling translation slots and should be release once the PA gets produced. The patch fixes this mismatch by restoring the resource release in the right place (while keeping the acquire in the constructor) and by adding a pendingMemAccess counter, which is keeping track of a complete device memory request (translation + final access) and will be used by the draining logic Change-Id: I708fe2d0b6c96ed46f3f4f9a0512f8c1cc43a56c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Adrian Herrera <adrian.herrera@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20260 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-05dev-arm: Implement invalidateASID in SMMUv3 WalkCacheJan-Peter Larsson
This patch fixes a bug where issuing a invalidate-by-ASID command (CMD_TLBI_NH_ASID) to the SMMU would cause Gem5 to crash. Change-Id: I5b8343a17e43762fe3917560ae401a20be1e05b8 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20259 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-05dev-arm: Implement invalidateVA/VAA in SMMUv3 WalkCacheAdrian Herrera
This patch implements VA/VAA invalidations in the SMMUv3 model. As per SMMUv3.0 spec, if leaf bit is specified in the invalidation command, only leaf entries within the walk cache need to be invalidated, otherwise entries with intermediate translations are also invalidated. Change-Id: I0eb1e1f1d8c00671a3c23d2a8fb756f2020d8d46 Reviewed-by: Michiel van Tol <michiel.vantol@arm.com> Reviewed-by: Marc Mari Barcelo <marc.maribarcelo@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20258 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-04dev: Templatize PioPort.Gabe Black
When creating a base class which needs to be a SimObject, it's necessary to decide ahead of time whether to use PioDevice or BasicPioDevice in the hierarchy because they inherit from SimObject. If they were added into the hierarchy later, then the original class would inherit from SimObject, as would PioDevice. That would create a diamond inheritance structure which would require virtual inheritance, and that's a can of worms we'd rather not get into. A big part of the PioPort mechanism is the PioPort itself which holds a pointer to its parent device and delegates reads/writes to it. It does that with a PioDevice pointer, and PioDevice declares virtual functions for all the callbacks the port can call into. Instead of that, this change templatizes PioPort based on the class of the device that holds it. That will let you use a PioPort on *any* class, as long as it has the methods PioPort depends on. That removes the need to create an inheritance diamond to add a PioPort down the line since PioDevice is no longer strictly required. The PioDevice and BasicPioDevice classes are still around since they still provide some additional functionality and there are existing classes which depend on them. Change-Id: I753afc1e0fa54b91217d54c1f8743c150537e960 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20568 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-27cpu, dev, mem: Use the new Port methods.Gabe Black
Use getPeer, takeOverFrom, and << to simplify the use of ports in some areas. Change-Id: Idfbda27411b5d6b742f5e4927894302ea6d6a53d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20235 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-08-26dev-arm: Fix GICv3 ITS indexing errorGiacomo Travaglini
Table walks were not considering the entry size when evaluating the address. Change-Id: Ica6bf6d88632985ee8ed120448b32e0f7e918a8a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20329 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-26dev-arm: Fix GITS_BASER initialization/accessGiacomo Travaglini
The patch is fixing/improving GITS_BASER registers initialization. * Not using reserved table types anymore (GITS_BASER.TYPE) * Using write mask for handling WI bits Change-Id: Ibe24667fdf22b42b86496167c19fc00bbb0ba191 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20328 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-22dev-arm: Start using GITS_CTLR.quiescent bitGiacomo Travaglini
The GITS_CTLR.quiescent bit is used by priviledged sw to check when the ITS has finished draining its state (all pending translations/table walks have ended) once it has been disabled (by setting the GITS_CTLR.enable bit to 0). This patch is modelling this behaviour by * Changing the reset state to enable=0, quiescent=1 * Making the GITS_CTLR.quiescent bit RO * Updating the bit once a new translation/command is being processed (quiescent=0) and when there are no pending translation/commands (quiescent=1) Change-Id: I7cfe94b25d603400364b1cdfc2d2397acf5dfad8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20257 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-22dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR/BASER)Giacomo Travaglini
For those registers (GITS_CWRITER, GITS_READR and GITS_CBASER) Bits [63:32] and bits [31:0] are accessible separately. Change-Id: Ibf60b5e4fd20efb21a63570e6012862e37946877 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20256 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-22dev-arm,system-arm: missing GICv3 ranges propertyAdrian Herrera
This patch adds the device tree "ranges" property to GICv3 for the VExpress_GEM5_V2 platform. It is also included in the GICv3 DTB auto generation. This allows the GICv3 ITS to be specified in the device tree. Change-Id: I00e1bb0fd45521e34820c0a23ddf047afec7aa4c Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20255 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20dev-arm: Add redistributor-stride property to GICv3Giacomo Travaglini
This is needed since by default the model is assuming a GICv4 memory layout. Change-Id: Ic64e6a488cc1a43a56ce28f6d11b8868df102aa0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20248 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-06 06:18:46 +0000