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AgeCommit message (Expand)Author
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-25dev-arm: Move GICv3 (Re)Ditributor address in Realview.pyGiacomo Travaglini
2019-04-25dev-arm: Limit number of max PE in GICv3 to 128Giacomo Travaglini
2019-04-25dev-arm: Add GICv4 extension switch in GICv3Giacomo Travaglini
2019-04-25dev-arm: Check for maximum number of supported PE in GICv3Giacomo Travaglini
2019-04-24dev: Use the new Port role mechanism to make an EtherInt Port type.Gabe Black
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
2019-03-27dev-arm: Rename GIC maintenance interrupt from ppint to maint_intGiacomo Travaglini
2019-03-27dev-arm: Fix GICv3 overflow for INTID > 256Giacomo Travaglini
2019-03-27dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)Giacomo Travaglini
2019-03-26dev-arm: Set/Unset dma coherent mode from pythonGiacomo Travaglini
2019-03-23misc: missing override specifierAndrea Mondelli
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-19mem: Move bind() and unbind() into the Port class.Gabe Black
2019-03-15dev: Make EtherInt inherit from Port.Gabe Black
2019-03-15dev: Make the EtherDevice class inherit EtherObject.Gabe Black
2019-03-15dev: Turn EtherObject into an interface class.Gabe Black
2019-03-14dev-arm: cleanup of gicv3 CPU interface code and fixesJairo Balart
2019-03-12dev-arm: cleanup of gicv3 codeJairo Balart
2019-03-01dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on readsGiacomo Travaglini
2019-03-01dev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping on readsGiacomo Travaglini
2019-02-18dev-arm: LPI support for GICv3. This doesn't include an ITS model.Jairo Balart
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2019-02-07configs, arch-arm: Using AddrRange for Realview mem_regionsGiacomo Travaglini
2019-02-01dev, arm: Removed contextId variableAnouk Van Laer
2019-01-24dev-arm: fix --generate-dtb for ARMCiro Santilli
2019-01-22arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.Gabe Black
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2019-01-10dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 supportJairo Balart
2019-01-10dev-arm: Add a GICv3 modelJairo Balart
2019-01-04dev, arm: Warn on PL011 DMA disableJan-Peter Larsson
2019-01-04dev-arm: Added VGIC GICV_IIDR responseAnouk Van Laer
2019-01-04dev-arm: Implement GIC-400 model from GicV2Giacomo Travaglini
2019-01-04dev-arm: Move VGic from Realview.py to Gic.pyGiacomo Travaglini
2019-01-04dev-arm: Added unimplemented GICv2 GICC_DIRAnouk Van Laer
2018-10-17dev: Remove using namespace TheISA in uart8250.cc.Gabe Black
2018-10-17dev: Explicitly specify the endianness for packet accessors.Gabe Black
2018-10-17dev: Build most of the networking devices in the NULL_ISA build.Gabe Black
2018-10-17dev: Build the PCI device models even in NULL_ISA builds.Gabe Black
2018-10-17dev-arm: Don't panic when EOIR a non active PPIAdrien Pesle
2018-10-17dev-arm: Fix Gicv2 distributor group registerAdrien Pesle
2018-10-12alpha: Use little endian packet accessors.Gabe Black
2018-10-12sparc: Use big endian packet accessors.Gabe Black
2018-10-12arm: Use little endian packet accessors.Gabe Black
2018-10-12x86: Use little endian packet accessors.Gabe Black
2018-10-12dev: Include the platform base class even in NULL_ISA builds.Gabe Black
2018-10-08dev, arm: remove the RealViewEB platformCiro Santilli
2018-10-01dev-arm: Enable FIQ signaling for Group0 interrupts in GICv2Giacomo Travaglini
2018-10-01dev-arm: Create postFiq events for GICv2Giacomo Travaglini
2018-10-01dev-arm: Implement GICv2 GICD_IGROUPR registerGiacomo Travaglini
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