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2019-04-28mem: Minimize the use of MemObject.Gabe Black
MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed. Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-25dev-arm: Move GICv3 (Re)Ditributor address in Realview.pyGiacomo Travaglini
Base addresses for GICv3's Distributor and Redistributors are implementation defined: they depend on the platform rather than the model. This patch is then moving dist_addr and redist_addr initialization in Realview.py Change-Id: I1246df500262f4d3d5a38e62d0240945f90941ee Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18393 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Limit number of max PE in GICv3 to 128Giacomo Travaglini
This is needed since there is a problem in the memory layout of VExpress_GEM5_V2 as it is: having 256KB pages is creating overlapping regions when reserving space for 256 PEs. GICv3 redistributors: 0x2c010000 - 0x30010000 PCI regions: 0x30000000 - 0x40000000 We fix this by cutting down the number of supported PEs to 128 Change-Id: I6e87f66a6150a441ccba298662b4548a4972dc40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18392 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Add GICv4 extension switch in GICv3Giacomo Travaglini
This is currently used only for determining which is the correct size of redistributors in memory (256KB in GICv4 and 128KB in GICv3) Change-Id: I2c07005e97167fde03548313c9927176788f31dd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18391 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25dev-arm: Check for maximum number of supported PE in GICv3Giacomo Travaglini
This is currently set to 256 Change-Id: If7bb2847c22f29bfa0cb4ebf4a7984ee43ab4e29 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18390 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-24dev: Use the new Port role mechanism to make an EtherInt Port type.Gabe Black
This type always uses the same "ETHERNET" role, and all connections are symmetric and self compatible. Change-Id: I1d060f8c098d52ae9f65c052f816bc813590ff9c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18171 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27dev-arm: Rename GIC maintenance interrupt from ppint to maint_intGiacomo Travaglini
ppint is a generic name which only reflects Arm recommendation of assigning the maintanance interrupt to a PPI (numbered 25) Change-Id: Ic5abb6ed50817ad2d165b5df46dd989eb195a9db Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17628 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27dev-arm: Fix GICv3 overflow for INTID > 256Giacomo Travaglini
SPIs can get to a maximum number of 1023, so that an uint8_t is not capable of representing all of them. Change-Id: I7a2c43b41ac93eabdfcf8311681240416b954177 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17631 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-27dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)Giacomo Travaglini
For SGIs and PPIs: * When ARE is 1 (only value supported in gem5) for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case. Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-26dev-arm: Set/Unset dma coherent mode from pythonGiacomo Travaglini
With this patch it will be possible to automatically enable/disable the dma-coherent property for the GenericArmPciHost autogenerated DTB. This has been done by adding the _dma_coherent param. Change-Id: I1759fced74e42410462637ca77997a351314a90a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16748 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-23misc: missing override specifierAndrea Mondelli
Missing specifier of overridden virtual function declared in sim_object.hh Removed redundant "virtual" keyword Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19mem: Move bind() and unbind() into the Port class.Gabe Black
These are now pure virtual methods which more specialized port subclasses will need to implement. The SlavePort class implements them by ignoring them and then providing parallel functions for the MasterPort to call. The MasterPort's methods do basically what they did before, except now bind() uses dynamic cast to check if its peer is of the appropriate type and also to convert it into that type before connecting to it. Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17038 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-15dev: Make EtherInt inherit from Port.Gabe Black
This way a common function can return EtherInt (and master and slave ports). Change-Id: I1215baaad918ef0352b228877241b2b6dd2503fc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17035 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-15dev: Make the EtherDevice class inherit EtherObject.Gabe Black
This avoids having to define two parallel versions of the getEthPort function, and the complex dynamic_cast macrame in connectPorts(). Change-Id: I24c09864005ff39a049e50d7245ff17e9480edea Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17029 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-15dev: Turn EtherObject into an interface class.Gabe Black
This class used to drive from SimObject so that it could be derived from to get both the interface and SimObject while still using single inheritance. With this change, EtherObject is now just an interface class with only one pure virtual function which can be inherited alongside SimObject. This makes it more flexible so that it can be used in places where you might want a different inheritance hierarchy, for instance to inherit from MemObject. Change-Id: I0f07664d104eed012cf4ce6e30c416ada19505a7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17028 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-14dev-arm: cleanup of gicv3 CPU interface code and fixesJairo Balart
Change-Id: I4643140f60da4dc9179b5bfed1e3ddd7c2f23091 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16484 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-12dev-arm: cleanup of gicv3 codeJairo Balart
Change-Id: I9aba90022f6408838c4ab87c6b90bba438752e53 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16222 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-01dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on readsGiacomo Travaglini
Reading ICV_PMR_EL1 should return the value the VMCR_EL2.VPMR bits which are aliased to the register. Change-Id: Id3e6dfb196f3726edaa3eddb244765598ed62334 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16545 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-01dev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping on readsGiacomo Travaglini
Reading ICV_IGRPEN<n>_EL1 should return the value of VMCR_EL2.VENG0 and VMCR_EL2.VENG1 bits. Change-Id: Ia5d748cf60ba074cccf4c127ac479c5cb881773d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16544 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-18dev-arm: LPI support for GICv3. This doesn't include an ITS model.Jairo Balart
Change-Id: Ia2c02cca4f95672d6361fba16201a56e2047ddb7 Reviewed-on: https://gem5-review.googlesource.com/c/16142 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files. Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-07configs, arch-arm: Using AddrRange for Realview mem_regionsGiacomo Travaglini
Physical memory ranges are now saved in Realview objects as pairs of addresses (start address and size). This patch is substituting them with a single AddrRange object. Change-Id: I02d25d557c5c54d062f0dccef8ede45744d0ce6b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16206 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-01dev, arm: Removed contextId variableAnouk Van Laer
The contextId variable is only used by the debug flag and will prevent a more optimised binary (i.e. fast) from compiling. Change-Id: I6cefb5bc06d0d4b415df62f1278db53ba309fb87 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16042 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-24dev-arm: fix --generate-dtb for ARMCiro Santilli
Was failing with: NameError: global name 'FdtNode' is not defined The problem was introduced at: 75831ce5b7880b67c1aa2e0871ce16d5c01cadc7 Change-Id: I7e2ce0e5311e7814229945b9f4e7318a8652dc1f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15875 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.Gabe Black
Other dev code was already switched over. This code was written before the switch over (or unaware of it), and checked in after. Change-Id: Ibb9e9e4300d01cc46e4dae668274debc2a4989ba Reviewed-on: https://gem5-review.googlesource.com/c/15755 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are some remaining types, specifically the vector registers and the CCReg. I'm less familiar with these new types of registers, and so will look at getting rid of them at some later time. Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b Reviewed-on: https://gem5-review.googlesource.com/c/13624 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-10dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 supportJairo Balart
Change-Id: I6fd14138d94654e8e60cde08239ea9a50fc19eb7 Reviewed-on: https://gem5-review.googlesource.com/c/14255 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-10dev-arm: Add a GICv3 modelJairo Balart
Change-Id: Ib0067fc743f84ff7be9f12d2fc33ddf63736bdd1 Reviewed-on: https://gem5-review.googlesource.com/c/13436 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-04dev, arm: Warn on PL011 DMA disableJan-Peter Larsson
The PL011 spec specifies a DMACR register at offset 0x48, which isn't implemented in the model. Currently any attempt to access the register results in a panic. This change swaps the panic for a warning only when software writes into DMACR to disable DMA, keeping the panic otherwise. Change-Id: I04586b52df8d5d174536276fd7ae19e77ff4681a Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15279 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Added VGIC GICV_IIDR responseAnouk Van Laer
Change-Id: I60e8eadbbbf07c0f8b726213fd580aeb0dd0e00b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15278 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Implement GIC-400 model from GicV2Giacomo Travaglini
Implementation registers for the GICv2 model currently hold values referring to a GIC-400 implementation. This patch is making them parametrizable so that it is possible to instantiate a GIC-400 model. The patch is also modifying Realview platform to use new GIC-400 model in lieau of GICv2. Change-Id: I446db8c796ee3c2708af91e9139f0a6e7947321b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15277 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Move VGic from Realview.py to Gic.pyGiacomo Travaglini
Change-Id: I17f2fb6be2435d4601263e7f68a0582e0cc70838 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15276 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Added unimplemented GICv2 GICC_DIRAnouk Van Laer
This GICC CPU register is not implemented but just gives a warning. Change-Id: I7630aa1df78dde5cf84a87e26cd580b00b283673 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15275 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Remove using namespace TheISA in uart8250.cc.Gabe Black
Nothing in that file is in the TheISA namespace, so there's no reason to use using on it. Change-Id: I279c27af86509f75ac4e340956381041a0dbcdc4 Reviewed-on: https://gem5-review.googlesource.com/c/13537 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Explicitly specify the endianness for packet accessors.Gabe Black
Generally speaking, the endianness of the data devices provide or accept is dependent on the device and not the ISA the system executes. This change makes the devices in dev pick an endianness rather than using the guest's. For the ISA bus and the UART, accesses are byte sized and so endianness doesn't matter. The ISA and PCI busses and the devices which use them are defined to be little endian. Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f Reviewed-on: https://gem5-review.googlesource.com/c/13462 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Build most of the networking devices in the NULL_ISA build.Gabe Black
The only part of these devices which are incompatible with other ISAs, with the possible exception of endianness transformation, is that the dist_iface implementation refers to ThreadContext methods and that class is heavily tied to the guest ISA. Only those few lines are excluded in a NULL_ISA build. Change-Id: Ic6d643fdbb792d0a996a37d75e027c5ce0ecd460 Reviewed-on: https://gem5-review.googlesource.com/c/13469 Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Build the PCI device models even in NULL_ISA builds.Gabe Black
There are some minor ISA dependencies in the PCI device models, specifically that they use the set<> accessors on the packet objects. This actually compiles fine because the NULL ISA claims to be little endian, but really these accessors should be changed to use little endian all the time since that's what PCI is defined to use, not the guest endianness. The other types of accessors, specifically the ones that default to what the guest wants, should be excluded when building NULL_ISA, and, pending other dependencies, the NULL_ISA should no longer have an endianness associated with it. Change-Id: I0739122dbf67d109e7959553a1eff0239b090ca4 Reviewed-on: https://gem5-review.googlesource.com/c/13468 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev-arm: Don't panic when EOIR a non active PPIAdrien Pesle
GIC architecture specification says that writing EOIR with a not active irq it is an unpredictable behavior. So, just warn when it happens for a PPI case, like it is already done in SPI case. Change-Id: Icb1b8f5690d5e87b15c3b0fe2ca0d37fdd4085ee Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13556 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev-arm: Fix Gicv2 distributor group registerAdrien Pesle
For each bit in GICD_IGROUPR: value 0 means corresponding irq is group0 value 1 means corresponding irq is group 1. Change-Id: I15699d4bc89ff3df0e0bdb41154c0d0989dc2f63 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13555 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-12alpha: Use little endian packet accessors.Gabe Black
We know data is little endian, so we can use those accessors explicitly. Change-Id: Ieb9c1eb8a4fec31ee69cbbfd8c1afdf9f64de366 Reviewed-on: https://gem5-review.googlesource.com/c/13459 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12sparc: Use big endian packet accessors.Gabe Black
We know data is big endian, so we can use those accessors explicitly. Change-Id: I06fe35254433b20db05f5f10d0ca29a44d47c301 Reviewed-on: https://gem5-review.googlesource.com/c/13458 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12arm: Use little endian packet accessors.Gabe Black
We know data is little endian, so we can use those accessors explicitly. Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45 Reviewed-on: https://gem5-review.googlesource.com/c/13457 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-12x86: Use little endian packet accessors.Gabe Black
We know data is little endian, so we can use those accessors explicitly. Change-Id: I09aa7f1e525ad1346e932ce4a772b64bf59dc350 Reviewed-on: https://gem5-review.googlesource.com/c/13456 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12dev: Include the platform base class even in NULL_ISA builds.Gabe Black
These classes don't have any ISA specific aspects. Change-Id: Ifefb12d23e4aee8e3fd56f0a1eb3d9ad00e733a0 Reviewed-on: https://gem5-review.googlesource.com/c/13467 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-08dev, arm: remove the RealViewEB platformCiro Santilli
This is an old platform, and we haven't had official Linux kernel configs for it in a while, so we've decided to deprecate it. Furthermore, trying to use it fails with: object 'RealViewEB' has no attribute 'pci_host' and the last commit in the class happened two years ago, which indicates that no one has been using it. Change-Id: Icc674b00b152eb3246e05141dbaf2624cc720f21 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12471 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01dev-arm: Enable FIQ signaling for Group0 interrupts in GICv2Giacomo Travaglini
Change-Id: Iafaf26344a26eade60c08dd2c0d716af14d9b328 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12948 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01dev-arm: Create postFiq events for GICv2Giacomo Travaglini
GICv2 is signaling IRQs only to the CPU. This patch is adding the capability of scheduling FIQs. Change-Id: I395afc83eb8d58cfd32cd93372bcb6f804364ef5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12947 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01dev-arm: Implement GICv2 GICD_IGROUPR registerGiacomo Travaglini
This patch is implementing GICD_IGROUPR register. Change-Id: I1626f61fbf7deec9c81d8d2c135f1d6c0c4eb891 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12946 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-07 02:11:26 +0000