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2019-01-22arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.Gabe Black
Other dev code was already switched over. This code was written before the switch over (or unaware of it), and checked in after. Change-Id: Ibb9e9e4300d01cc46e4dae668274debc2a4989ba Reviewed-on: https://gem5-review.googlesource.com/c/15755 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are some remaining types, specifically the vector registers and the CCReg. I'm less familiar with these new types of registers, and so will look at getting rid of them at some later time. Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b Reviewed-on: https://gem5-review.googlesource.com/c/13624 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-10dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 supportJairo Balart
Change-Id: I6fd14138d94654e8e60cde08239ea9a50fc19eb7 Reviewed-on: https://gem5-review.googlesource.com/c/14255 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-10dev-arm: Add a GICv3 modelJairo Balart
Change-Id: Ib0067fc743f84ff7be9f12d2fc33ddf63736bdd1 Reviewed-on: https://gem5-review.googlesource.com/c/13436 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-04dev, arm: Warn on PL011 DMA disableJan-Peter Larsson
The PL011 spec specifies a DMACR register at offset 0x48, which isn't implemented in the model. Currently any attempt to access the register results in a panic. This change swaps the panic for a warning only when software writes into DMACR to disable DMA, keeping the panic otherwise. Change-Id: I04586b52df8d5d174536276fd7ae19e77ff4681a Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15279 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Added VGIC GICV_IIDR responseAnouk Van Laer
Change-Id: I60e8eadbbbf07c0f8b726213fd580aeb0dd0e00b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15278 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Implement GIC-400 model from GicV2Giacomo Travaglini
Implementation registers for the GICv2 model currently hold values referring to a GIC-400 implementation. This patch is making them parametrizable so that it is possible to instantiate a GIC-400 model. The patch is also modifying Realview platform to use new GIC-400 model in lieau of GICv2. Change-Id: I446db8c796ee3c2708af91e9139f0a6e7947321b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15277 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Move VGic from Realview.py to Gic.pyGiacomo Travaglini
Change-Id: I17f2fb6be2435d4601263e7f68a0582e0cc70838 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15276 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-04dev-arm: Added unimplemented GICv2 GICC_DIRAnouk Van Laer
This GICC CPU register is not implemented but just gives a warning. Change-Id: I7630aa1df78dde5cf84a87e26cd580b00b283673 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15275 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Remove using namespace TheISA in uart8250.cc.Gabe Black
Nothing in that file is in the TheISA namespace, so there's no reason to use using on it. Change-Id: I279c27af86509f75ac4e340956381041a0dbcdc4 Reviewed-on: https://gem5-review.googlesource.com/c/13537 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Explicitly specify the endianness for packet accessors.Gabe Black
Generally speaking, the endianness of the data devices provide or accept is dependent on the device and not the ISA the system executes. This change makes the devices in dev pick an endianness rather than using the guest's. For the ISA bus and the UART, accesses are byte sized and so endianness doesn't matter. The ISA and PCI busses and the devices which use them are defined to be little endian. Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f Reviewed-on: https://gem5-review.googlesource.com/c/13462 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Build most of the networking devices in the NULL_ISA build.Gabe Black
The only part of these devices which are incompatible with other ISAs, with the possible exception of endianness transformation, is that the dist_iface implementation refers to ThreadContext methods and that class is heavily tied to the guest ISA. Only those few lines are excluded in a NULL_ISA build. Change-Id: Ic6d643fdbb792d0a996a37d75e027c5ce0ecd460 Reviewed-on: https://gem5-review.googlesource.com/c/13469 Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev: Build the PCI device models even in NULL_ISA builds.Gabe Black
There are some minor ISA dependencies in the PCI device models, specifically that they use the set<> accessors on the packet objects. This actually compiles fine because the NULL ISA claims to be little endian, but really these accessors should be changed to use little endian all the time since that's what PCI is defined to use, not the guest endianness. The other types of accessors, specifically the ones that default to what the guest wants, should be excluded when building NULL_ISA, and, pending other dependencies, the NULL_ISA should no longer have an endianness associated with it. Change-Id: I0739122dbf67d109e7959553a1eff0239b090ca4 Reviewed-on: https://gem5-review.googlesource.com/c/13468 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev-arm: Don't panic when EOIR a non active PPIAdrien Pesle
GIC architecture specification says that writing EOIR with a not active irq it is an unpredictable behavior. So, just warn when it happens for a PPI case, like it is already done in SPI case. Change-Id: Icb1b8f5690d5e87b15c3b0fe2ca0d37fdd4085ee Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13556 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-17dev-arm: Fix Gicv2 distributor group registerAdrien Pesle
For each bit in GICD_IGROUPR: value 0 means corresponding irq is group0 value 1 means corresponding irq is group 1. Change-Id: I15699d4bc89ff3df0e0bdb41154c0d0989dc2f63 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13555 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-12alpha: Use little endian packet accessors.Gabe Black
We know data is little endian, so we can use those accessors explicitly. Change-Id: Ieb9c1eb8a4fec31ee69cbbfd8c1afdf9f64de366 Reviewed-on: https://gem5-review.googlesource.com/c/13459 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12sparc: Use big endian packet accessors.Gabe Black
We know data is big endian, so we can use those accessors explicitly. Change-Id: I06fe35254433b20db05f5f10d0ca29a44d47c301 Reviewed-on: https://gem5-review.googlesource.com/c/13458 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12arm: Use little endian packet accessors.Gabe Black
We know data is little endian, so we can use those accessors explicitly. Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45 Reviewed-on: https://gem5-review.googlesource.com/c/13457 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-12x86: Use little endian packet accessors.Gabe Black
We know data is little endian, so we can use those accessors explicitly. Change-Id: I09aa7f1e525ad1346e932ce4a772b64bf59dc350 Reviewed-on: https://gem5-review.googlesource.com/c/13456 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-10-12dev: Include the platform base class even in NULL_ISA builds.Gabe Black
These classes don't have any ISA specific aspects. Change-Id: Ifefb12d23e4aee8e3fd56f0a1eb3d9ad00e733a0 Reviewed-on: https://gem5-review.googlesource.com/c/13467 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-08dev, arm: remove the RealViewEB platformCiro Santilli
This is an old platform, and we haven't had official Linux kernel configs for it in a while, so we've decided to deprecate it. Furthermore, trying to use it fails with: object 'RealViewEB' has no attribute 'pci_host' and the last commit in the class happened two years ago, which indicates that no one has been using it. Change-Id: Icc674b00b152eb3246e05141dbaf2624cc720f21 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12471 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01dev-arm: Enable FIQ signaling for Group0 interrupts in GICv2Giacomo Travaglini
Change-Id: Iafaf26344a26eade60c08dd2c0d716af14d9b328 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12948 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01dev-arm: Create postFiq events for GICv2Giacomo Travaglini
GICv2 is signaling IRQs only to the CPU. This patch is adding the capability of scheduling FIQs. Change-Id: I395afc83eb8d58cfd32cd93372bcb6f804364ef5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12947 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01dev-arm: Implement GICv2 GICD_IGROUPR registerGiacomo Travaglini
This patch is implementing GICD_IGROUPR register. Change-Id: I1626f61fbf7deec9c81d8d2c135f1d6c0c4eb891 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12946 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01dev-arm: Fix GICv2 cpu interrupt enable flagGiacomo Travaglini
Read/WriteCpu methods in the GICv2 are accessing the GICC_CTRL register as if writing any non-zero value to the register will enable IRQ signaling to the CPU. Instead, only the 2 least significant bits control group0/group1 enablement. This patch is renaming GICC_CTRL underlying data buffer from cpuEnabled to cpuControl and it is making it an array of uint32_t instead of bool. cpuEnabled now becomes a method and checks if GICC_CTRL.EnableGrp0 or GICC_CTRL.EnableGrp0 are set. Change-Id: I40f0b3c52c40abd482a856f032bf3686f96ef641 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12945 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01dev-arm: Add basic support for level sensitive SPIs in GICv2Adrien Pesle
For level sensitive interrupt IRQ line must be cleared when interrupt is deasserted. This is not the case for edge-trigerred interrupt. Change-Id: Ib1660da74a296750c0eb9e20878d4ee64bd23130 Reviewed-on: https://gem5-review.googlesource.com/12944 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-28dev-arm: Make CpuLocalTimer use standard ArmInterruptPinGiacomo Travaglini
Change-Id: I8c4eb9389b47df8cdf1eec966bb2c9da85a7a7c8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12744 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-28dev-arm: Take into account PPI enable bitGiacomo Travaglini
When checking for PPIs to send to the cpu in the PL390 GIC we were forwarding any pending PPI regardless of their masking in the distributor. Change-Id: I2e294abeca733cca95cd0deeb9659c7d3d9d8734 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12624 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-18dev, arm: fix error class-memaccess with GCC >= 8.1Maurice Becker
From GCC 8.1 on GCC issues a warning when using memset et al on structs and classes. With the way gem5 builds, this actually prevents successful builds. Instead of using a pointer with SCSIReply as type, we cast to a void pointer to avoid the message. On the way we wrap the memset call into a method of SCSIReply called reset for better code readability. Signed-off-by: Maurice Becker <madnaurice@googlemail.com> Change-Id: I3ed3fd9714be5d253aba01ca00b1863e1ae5cb68 Reviewed-on: https://gem5-review.googlesource.com/12685 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-18Pl011: Added registers UART_RSR/UART_ECRMaurice Becker
UART_RSR shows errors with the transmission and UART_ECR can clear those (according to PL011 Technical Reference Manual Revision r1p4). As these transmission errors never occur, they are implemented as RAZ/WI. Both registers exist at the same offset 0x004. RSR is read-only, ECR is write-only. Signed-off-by: Maurice Becker <madnaurice@googlemail.com> Change-Id: Ia9d13c90c65feccf3ecec36a782170755b1e1c02 Reviewed-on: https://gem5-review.googlesource.com/12686 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12dev-arm: fix build to missing Pl390 to Gicv2 renameCiro Santilli
Change-Id: I6756f2c789aaca410d201aa64147443b66afee39 Reviewed-on: https://gem5-review.googlesource.com/12645 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12config, dev-arm: Fix UART handling baremetal modeCiro Santilli
fs.py in baremetal mode currently fails for the VExpress_GEM5_V1 platform due to inconsistent UART naming with error message: AttributeError: object 'VExpress_GEM5_V1' has no attribute 'uart' Consistently name keep all UARTs in the Arm platforms in a vector named 'uart' or as a single device named 'uart'. Update the configuration scripts to reflect the fact that 'uart' can be a vector. Change-Id: I20b8dbac794d6a9be19b6ce8c335a097872132fb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12473 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12dev-arm: rename Pl390 to GicV2Ciro Santilli
The Pl390 model has evolved and acquired a lot of the features from GICv2, which means that the name is no longer appropriate. Rename it to GICv2 since this is more representative of the supported features. GICv2 is backwards compatible with the older Pl390, so we decided to simply rename the class to represent both GICv2 and older interfaces such as the instead of creating a new separate one. Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12492 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12dev-arm: improve Pl390 parametersCiro Santilli
Remove default dist_addr and cpu_addr register addresses since those are purely platform specific. Parametrize the cpu_size parameter. RealViewPBX has the Gic CPU and distributor base too close for the newer CPU size of 0x2000, leading to overlap. This was introduced in I90a9f669a46a37d79c6cc542087cf91f2044f104 and makes using RealViewPBX fail with: fatal: system.membus has two ports responding within range [0x1f000100 : 0x1f0020ff]: system.realview.gic.pio system.realview.gic.pio Change-Id: Ic6c0e6b3d4705ff369eb739d54a1173a47819b7d Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12491 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-11net: Fix a bug when receiving fragamented packetsPin-Yen Lin
In the previous implementation, the function EtherTap::recvReal will only read one packet when received some ``interrupt'' (explicitly, when async_IO set to true). When someone tries to send a large message to the simulated device, the message will be divided to several packets due to packet fragmentation. In this situation recvReal will only read one packet and left the other packets in the buffer. This significantly increases the networking latency. So before reading from socket, I change the socket into non-blocking mode and keep reading from it until there's no packet left. Change-Id: Ieb94a8532cd3994862b6f3eb9474caf7ccf617da Reviewed-on: https://gem5-review.googlesource.com/12338 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-10dev-arm: Make GenericTimer use standard ArmInterruptPinGiacomo Travaglini
This patch is deleting the custom ArchTimer::Interrupt implementation in favour of the standard ArmInterruptPin. Change-Id: I5aa5661e48834398bd7aae15df9578b8db5c8da3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12402 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-10dev-arm: Factory SimObject for generating ArmInterruptPinGiacomo Travaglini
With this patch the python ArmInterruptPin SimObject matches to the C++ ArmInterruptPinGen. The latter is in charge of generating the ArmInterruptPin (which is not a SimObject anymore). This is meant to ease the generation of ArmInterruptPins: by not being SimObjects we are not forced to instantiate them in the configuration script; we can generate them dynamically instead throughout simulation. Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12401 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-10dev, arm: Add misc reg tracing to the generic timerAndreas Sandberg
Change-Id: Ice9376b8eb42423679b0191910e8c980f8017f88 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12398
2018-09-10dev-arm: Create a getter for ArmInterruptPin ID numberGiacomo Travaglini
A pin owner might want to know which is the irq number associated with the pin. Change-Id: I095393d4d25efe13eb2a75a0b0b055d386c2c126 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12298 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-07net: Fix a bug when handling IPv6 packetsPin-Yen Lin
When gem5 runs with the networking support, it will run into an assertion fail and aborted. This is because it tries to calculate checksum for IPv6 packet and this makes the IpPtr pointer ``ip'' become NULL. For that there is functions and classes for IPv6 in base/inet.cc, I added IPv6 support for i8254xGBe.cc. Because IPv6 header does not have identification number, I ignored some of the debug messages using ip->id(). Change-Id: Ida5e36aefd2c5c26053f8152a0aac24191e7757c Reviewed-on: https://gem5-review.googlesource.com/12339 Reviewed-by: Earl Ou <shunhsingou@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-08-21dev, arm: Fix incorrect GIC address range sizesAndreas Sandberg
The GICv2 specifies that 8KiB of the memory map is allocated to the CPU interface and 4KiB is allocated to the distributor. The current distributor size is off by 1 and the CPU interface is completely off by a lot. Change-Id: I90a9f669a46a37d79c6cc542087cf91f2044f104 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11769
2018-08-21misc: Appease GCC 8Jason Lowe-Power
GCC 8 adds a number of new warnings to -Wall which generate errors. - Fix memset to 0 for structs by adding casts. - Fix cast with const when the const was ignored. - Fix catch a polymorphic type by value We now compile with GCC 8! Change-Id: Iab70ce11190eee67608fc25c0bedff170152b153 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/11949 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2018-07-17dev, arm: accept and ignore writes to GIC APRn registersCiro Santilli
Otherwise the Linux kernel v4.17 boot fails with error: Tried to write Gic cpu at offset 0xd0 Change-Id: Ie8063212c9e2b29e2e4766801b4b9538e9eccbf8 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11590 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-21dev-arm: Use recurseDeviceTree instead of custom in platformAndreas Sandberg
The platform code uses a custom mechanism to traverse the object hierarchy when generating device trees. This is highly undesirable since this breaks for common cases such as when SimObjects are stored in a list. Change-Id: I1b968e5fa1db62f1456e3c0ac3de47ab1299e58d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10781 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-15dev-arm: Fix the address range for some I/O devicesNikos Nikoleris
Previously, many devices were incorrecty configured to respond to an address range of size 0xfff. This changes fixes this and sets it to 0x1000. Change-Id: I4b027a27adf60ceae4859e287d7f34443b398752 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11116 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-14dev-arm: Add new VExpress_GEM5_V1_Base PlatformRohit Kurup
Add a new VExpress_GEM5_V1_Base Platform which configures basic on chip devices. The original VExpress_GEM5_V1 will inherit the Base and add more on chip devices (currently only the HDLCD). This change will make it possible to create variations of the base platform with different devices. Change-Id: I21f9bf4f6217d87e811ff777f630122593eef013 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10807 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-14dev-arm: Remove deprecated GIC test interfacesAndreas Sandberg
Change-Id: I4c5203b216387d9a4f041c7a00caea926e5cfca6 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10810
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-07dev-arm: Add a VirtIO MMIO device to VExpress_GEM5_V1Andreas Sandberg
Add an ARM-specific VirtIO MMIO device to the VExpress_GEM5_V1 platform. Change-Id: Id1e75398e039aad9d637f46f653cda9084d3d2fe Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2327
2018-06-07dev-arm: Add a MMIO transport interface for VirtIOAndreas Sandberg
The MMIO interface currently only supports a subset of version 0.9.5 of the VirtIO specification. It has the following known limitations: * The queue size hint (the QUEUE_NUM register) is ignored. * Queue alignment is assumed to be hard-coded to VirtQueue::ALIGN_SIZE (4096 bytes). * Only 4096 byte pages are currently supported. Change-Id: Ifd318f5e5bddab0b6a42d8c8af9ff2fbb477f98b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2326 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 10:11:14 +0000