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AgeCommit message (Expand)Author
2019-06-26dev-arm: pending SMMU transl update on constructor/destructorAdrian Herrera
2019-06-17dev-arm: Reapply GICv3 changes that were lost during refactoringGiacomo Travaglini
2019-06-06dev-arm: Implement a SMMUv3 modelStanislaw Czerniawski
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
2019-05-22dev-arm: Provide a GICv3 ITS ImplementationGiacomo Travaglini
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
2019-05-03dev: StreamID generation in DMA deviceGiacomo Travaglini
2019-05-02dev-arm: Store a PhysProxy port in Gicv3RedistGiacomo Travaglini
2019-05-02dev-arm: Add named variable for GICD_TYPER.IDBitsGiacomo Travaglini
2019-05-02dev-arm: Read correct version of ICC_BPR registerGiacomo Travaglini
2019-05-02dev-arm: Get a Gicv3Redistributor ptr from phys addressGiacomo Travaglini
2019-05-02dev-arm: Add several LPI methods in Gicv3RedistributorGiacomo Travaglini
2019-05-02dev-arm: Take LPIs into account when interacting with CPUIF regsGiacomo Travaglini
2019-05-02dev-arm: Fix GICv3 LPIs priority valueGiacomo Travaglini
2019-05-02dev-arm: Disable LPI Configuration Table cachingGiacomo Travaglini
2019-05-02dev-arm: Check EnableLPIs before checking for pending LPIsGiacomo Travaglini
2019-05-02dev-arm: GICv3 LPI tables are using physical addressesGiacomo Travaglini
2019-05-02dev-arm: Fix GICv3 LPI loopGiacomo Travaglini
2019-05-02dev-arm: Fix Bitwise operation in GICv3Giacomo Travaglini
2019-04-30sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-25dev-arm: Move GICv3 (Re)Ditributor address in Realview.pyGiacomo Travaglini
2019-04-25dev-arm: Limit number of max PE in GICv3 to 128Giacomo Travaglini
2019-04-25dev-arm: Add GICv4 extension switch in GICv3Giacomo Travaglini
2019-04-25dev-arm: Check for maximum number of supported PE in GICv3Giacomo Travaglini
2019-04-24dev: Use the new Port role mechanism to make an EtherInt Port type.Gabe Black
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
2019-03-27dev-arm: Rename GIC maintenance interrupt from ppint to maint_intGiacomo Travaglini
2019-03-27dev-arm: Fix GICv3 overflow for INTID > 256Giacomo Travaglini
2019-03-27dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)Giacomo Travaglini
2019-03-26dev-arm: Set/Unset dma coherent mode from pythonGiacomo Travaglini
2019-03-23misc: missing override specifierAndrea Mondelli
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-19mem: Move bind() and unbind() into the Port class.Gabe Black
2019-03-15dev: Make EtherInt inherit from Port.Gabe Black
2019-03-15dev: Make the EtherDevice class inherit EtherObject.Gabe Black
2019-03-15dev: Turn EtherObject into an interface class.Gabe Black
2019-03-14dev-arm: cleanup of gicv3 CPU interface code and fixesJairo Balart
2019-03-12dev-arm: cleanup of gicv3 codeJairo Balart
2019-03-01dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on readsGiacomo Travaglini
2019-03-01dev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping on readsGiacomo Travaglini
2019-02-18dev-arm: LPI support for GICv3. This doesn't include an ITS model.Jairo Balart
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2019-02-07configs, arch-arm: Using AddrRange for Realview mem_regionsGiacomo Travaglini
2019-02-01dev, arm: Removed contextId variableAnouk Van Laer
2019-01-24dev-arm: fix --generate-dtb for ARMCiro Santilli
2019-01-22arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.Gabe Black
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2019-01-10dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 supportJairo Balart
2019-01-10dev-arm: Add a GICv3 modelJairo Balart
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