Age | Commit message (Collapse) | Author |
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should configure their editors to not insert tabs
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same packet again.
It doesn't cause a problem currently, however with a different Memory Object it could cause
problems
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starts/ends as well as after read/write dmas
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actually finished.
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postedInterrupts statistics.
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When invoking several copies of m5 on the same machine at the same
time, there can be a race for TCP ports for the terminal connections
or remote gdb. Expose a function to disable those ports, and have the
regression scripts disable them. There are some SimObjects that have
no other function than to be used with ports (NativeTrace and
EtherTap), so they will panic if the ports are disabled.
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moderation not always delay if no interrupts have been posted for the ITR value.
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of those statistics to the e1000 model.
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Make sure variables are properly initialized and also make sure that
truth testing works properly.
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a packet to exist in multiple FIFOs if desired.
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--HG--
rename : src/dev/mips/MipsConsole.py => src/dev/mips/MipsBackdoor.py
rename : src/dev/mips/console.cc => src/dev/mips/backdoor.cc
rename : src/dev/mips/console.hh => src/dev/mips/backdoor.hh
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--HG--
rename : src/dev/alpha/AlphaConsole.py => src/dev/alpha/AlphaBackdoor.py
rename : src/dev/alpha/console.cc => src/dev/alpha/backdoor.cc
rename : src/dev/alpha/console.hh => src/dev/alpha/backdoor.hh
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--HG--
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
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--HG--
rename : src/dev/SimConsole.py => src/dev/Terminal.py
rename : src/dev/simconsole.cc => src/dev/terminal.cc
rename : src/dev/simconsole.hh => src/dev/terminal.hh
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"behind" the pci config magic ports.
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--HG--
extra : convert_revision : 8fb7d5fad5cb840f69c31aa8b331dbe09e46ee9d
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Make OutputDirectory::resolve() private and change the functions using
resolve() to instead use create().
--HG--
extra : convert_revision : 36d4be629764d0c4c708cec8aa712cd15f966453
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--HG--
extra : convert_revision : 3f93c17f647a6955dab861da211174de856ee02c
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--HG--
extra : convert_revision : a614373236fe75db6e6181fc152a02b541a131f3
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--HG--
extra : convert_revision : 1e7f5185654ed0845678c2169c702d3b977159ed
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--HG--
extra : convert_revision : c0416de5d88ca39f54494418768e68a93aa4f2aa
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--HG--
extra : convert_revision : 92918c05eb3363155d78889bdab17baa8eae9dca
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--HG--
extra : convert_revision : 2c6ffebbad04a21cef6ba3fbc1803218908a6c37
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--HG--
extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
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scheme.
--HG--
extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6
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--HG--
extra : convert_revision : a1f16bd82b6fbd5b6b5dc0f08b9e69858bea86ca
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--HG--
extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
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--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
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file with them all.
--HG--
extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
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--HG--
extra : convert_revision : 10ec3484647b3acb8e821f8520f97d535e41e861
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--HG--
extra : convert_revision : 7d64d3e78960f3bb937579f5d10937bed5f197be
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--HG--
extra : convert_revision : 3d95f6daa7f0e8e376d1a880f64c056619263885
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--HG--
extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
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--HG--
extra : convert_revision : fb973bcf13648876d5691231845dd47a2be50f01
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--HG--
extra : convert_revision : 14306d3cd79bbef7decdf2fd370ed7e7f2b10a93
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--HG--
extra : convert_revision : bfc0ac8e1c8a5d01d9fa5203184bbf99c8361da3
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--HG--
extra : convert_revision : 2c6710e01a4402793a2e0eafcc829df19d03dda3
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SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses
The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
--HG--
extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
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--HG--
extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
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parameters.
--HG--
extra : convert_revision : bd2214b28fb46a9a9e9e204e0539be33acb548ad
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--HG--
extra : convert_revision : 765b096785a77df9adc4791c9101b90696bd7be2
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way so a cache can handle partial block requests for i/o devices.
--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
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--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233
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