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Nothing in that file is in the TheISA namespace, so there's no reason
to use using on it.
Change-Id: I279c27af86509f75ac4e340956381041a0dbcdc4
Reviewed-on: https://gem5-review.googlesource.com/c/13537
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Generally speaking, the endianness of the data devices provide or
accept is dependent on the device and not the ISA the system
executes. This change makes the devices in dev pick an endianness
rather than using the guest's.
For the ISA bus and the UART, accesses are byte sized and so endianness
doesn't matter. The ISA and PCI busses and the devices which use them
are defined to be little endian.
Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f
Reviewed-on: https://gem5-review.googlesource.com/c/13462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The only part of these devices which are incompatible with other ISAs,
with the possible exception of endianness transformation, is that
the dist_iface implementation refers to ThreadContext methods and
that class is heavily tied to the guest ISA. Only those few lines are
excluded in a NULL_ISA build.
Change-Id: Ic6d643fdbb792d0a996a37d75e027c5ce0ecd460
Reviewed-on: https://gem5-review.googlesource.com/c/13469
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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There are some minor ISA dependencies in the PCI device models,
specifically that they use the set<> accessors on the packet objects.
This actually compiles fine because the NULL ISA claims to be little
endian, but really these accessors should be changed to use little
endian all the time since that's what PCI is defined to use, not
the guest endianness.
The other types of accessors, specifically the ones that default to
what the guest wants, should be excluded when building NULL_ISA, and,
pending other dependencies, the NULL_ISA should no longer have an
endianness associated with it.
Change-Id: I0739122dbf67d109e7959553a1eff0239b090ca4
Reviewed-on: https://gem5-review.googlesource.com/c/13468
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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GIC architecture specification says that writing EOIR with
a not active irq it is an unpredictable behavior.
So, just warn when it happens for a PPI case, like it is
already done in SPI case.
Change-Id: Icb1b8f5690d5e87b15c3b0fe2ca0d37fdd4085ee
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13556
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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For each bit in GICD_IGROUPR:
value 0 means corresponding irq is group0
value 1 means corresponding irq is group 1.
Change-Id: I15699d4bc89ff3df0e0bdb41154c0d0989dc2f63
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13555
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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We know data is little endian, so we can use those accessors
explicitly.
Change-Id: Ieb9c1eb8a4fec31ee69cbbfd8c1afdf9f64de366
Reviewed-on: https://gem5-review.googlesource.com/c/13459
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
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We know data is big endian, so we can use those accessors
explicitly.
Change-Id: I06fe35254433b20db05f5f10d0ca29a44d47c301
Reviewed-on: https://gem5-review.googlesource.com/c/13458
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
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We know data is little endian, so we can use those accessors
explicitly.
Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45
Reviewed-on: https://gem5-review.googlesource.com/c/13457
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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We know data is little endian, so we can use those accessors
explicitly.
Change-Id: I09aa7f1e525ad1346e932ce4a772b64bf59dc350
Reviewed-on: https://gem5-review.googlesource.com/c/13456
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
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These classes don't have any ISA specific aspects.
Change-Id: Ifefb12d23e4aee8e3fd56f0a1eb3d9ad00e733a0
Reviewed-on: https://gem5-review.googlesource.com/c/13467
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This is an old platform, and we haven't had official Linux kernel configs
for it in a while, so we've decided to deprecate it.
Furthermore, trying to use it fails with:
object 'RealViewEB' has no attribute 'pci_host'
and the last commit in the class happened two years ago, which indicates
that no one has been using it.
Change-Id: Icc674b00b152eb3246e05141dbaf2624cc720f21
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/12471
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: Iafaf26344a26eade60c08dd2c0d716af14d9b328
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12948
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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GICv2 is signaling IRQs only to the CPU. This patch is adding the
capability of scheduling FIQs.
Change-Id: I395afc83eb8d58cfd32cd93372bcb6f804364ef5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12947
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch is implementing GICD_IGROUPR register.
Change-Id: I1626f61fbf7deec9c81d8d2c135f1d6c0c4eb891
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12946
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Read/WriteCpu methods in the GICv2 are accessing the GICC_CTRL register
as if writing any non-zero value to the register will enable IRQ
signaling to the CPU. Instead, only the 2 least significant bits
control group0/group1 enablement. This patch is renaming GICC_CTRL
underlying data buffer from cpuEnabled to cpuControl and it is making it
an array of uint32_t instead of bool. cpuEnabled now becomes a method
and checks if GICC_CTRL.EnableGrp0 or GICC_CTRL.EnableGrp0 are set.
Change-Id: I40f0b3c52c40abd482a856f032bf3686f96ef641
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12945
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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For level sensitive interrupt IRQ line must be cleared when interrupt is
deasserted. This is not the case for edge-trigerred interrupt.
Change-Id: Ib1660da74a296750c0eb9e20878d4ee64bd23130
Reviewed-on: https://gem5-review.googlesource.com/12944
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I8c4eb9389b47df8cdf1eec966bb2c9da85a7a7c8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12744
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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When checking for PPIs to send to the cpu in the PL390 GIC we
were forwarding any pending PPI regardless of their masking
in the distributor.
Change-Id: I2e294abeca733cca95cd0deeb9659c7d3d9d8734
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12624
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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From GCC 8.1 on GCC issues a warning when using memset et al on structs and
classes. With the way gem5 builds, this actually prevents successful
builds.
Instead of using a pointer with SCSIReply as type, we cast to a void
pointer to avoid the message. On the way we wrap the memset call into a
method of SCSIReply called reset for better code readability.
Signed-off-by: Maurice Becker <madnaurice@googlemail.com>
Change-Id: I3ed3fd9714be5d253aba01ca00b1863e1ae5cb68
Reviewed-on: https://gem5-review.googlesource.com/12685
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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UART_RSR shows errors with the transmission and UART_ECR can clear
those (according to PL011 Technical Reference Manual Revision r1p4). As
these transmission errors never occur, they are implemented as RAZ/WI.
Both registers exist at the same offset 0x004. RSR is read-only, ECR is
write-only.
Signed-off-by: Maurice Becker <madnaurice@googlemail.com>
Change-Id: Ia9d13c90c65feccf3ecec36a782170755b1e1c02
Reviewed-on: https://gem5-review.googlesource.com/12686
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I6756f2c789aaca410d201aa64147443b66afee39
Reviewed-on: https://gem5-review.googlesource.com/12645
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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fs.py in baremetal mode currently fails for the VExpress_GEM5_V1 platform
due to inconsistent UART naming with error message:
AttributeError: object 'VExpress_GEM5_V1' has no attribute 'uart'
Consistently name keep all UARTs in the Arm platforms in a vector named
'uart' or as a single device named 'uart'. Update the configuration
scripts to reflect the fact that 'uart' can be a vector.
Change-Id: I20b8dbac794d6a9be19b6ce8c335a097872132fb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12473
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The Pl390 model has evolved and acquired a lot of the features from GICv2,
which means that the name is no longer appropriate. Rename it to GICv2
since this is more representative of the supported features.
GICv2 is backwards compatible with the older Pl390, so we decided to
simply rename the class to represent both GICv2 and older interfaces such
as the instead of creating a new separate one.
Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12492
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Remove default dist_addr and cpu_addr register addresses since those are
purely platform specific.
Parametrize the cpu_size parameter. RealViewPBX has the Gic CPU and
distributor base too close for the newer CPU size of 0x2000, leading to
overlap.
This was introduced in I90a9f669a46a37d79c6cc542087cf91f2044f104 and makes
using RealViewPBX fail with:
fatal: system.membus has two ports responding within range
[0x1f000100 : 0x1f0020ff]:
system.realview.gic.pio
system.realview.gic.pio
Change-Id: Ic6c0e6b3d4705ff369eb739d54a1173a47819b7d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12491
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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In the previous implementation, the function EtherTap::recvReal will only
read one packet when received some ``interrupt'' (explicitly, when async_IO
set to true). When someone tries to send a large message to the simulated
device, the message will be divided to several packets due to packet
fragmentation. In this situation recvReal will only read one packet and
left the other packets in the buffer. This significantly increases the
networking latency. So before reading from socket, I change the socket into
non-blocking mode and keep reading from it until there's no packet left.
Change-Id: Ieb94a8532cd3994862b6f3eb9474caf7ccf617da
Reviewed-on: https://gem5-review.googlesource.com/12338
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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This patch is deleting the custom ArchTimer::Interrupt implementation in
favour of the standard ArmInterruptPin.
Change-Id: I5aa5661e48834398bd7aae15df9578b8db5c8da3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12402
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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With this patch the python ArmInterruptPin SimObject matches to the
C++ ArmInterruptPinGen. The latter is in charge of generating
the ArmInterruptPin (which is not a SimObject anymore).
This is meant to ease the generation of ArmInterruptPins: by
not being SimObjects we are not forced to instantiate them
in the configuration script; we can generate them dynamically
instead throughout simulation.
Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12401
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: Ice9376b8eb42423679b0191910e8c980f8017f88
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12398
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A pin owner might want to know which is the irq number
associated with the pin.
Change-Id: I095393d4d25efe13eb2a75a0b0b055d386c2c126
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12298
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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When gem5 runs with the networking support, it will run into an assertion
fail and aborted. This is because it tries to calculate checksum for IPv6
packet and this makes the IpPtr pointer ``ip'' become NULL. For that there
is functions and classes for IPv6 in base/inet.cc, I added IPv6 support for
i8254xGBe.cc. Because IPv6 header does not have identification number, I
ignored some of the debug messages using ip->id().
Change-Id: Ida5e36aefd2c5c26053f8152a0aac24191e7757c
Reviewed-on: https://gem5-review.googlesource.com/12339
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The GICv2 specifies that 8KiB of the memory map is allocated to the
CPU interface and 4KiB is allocated to the distributor. The current
distributor size is off by 1 and the CPU interface is completely off
by a lot.
Change-Id: I90a9f669a46a37d79c6cc542087cf91f2044f104
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11769
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GCC 8 adds a number of new warnings to -Wall which generate errors.
- Fix memset to 0 for structs by adding casts.
- Fix cast with const when the const was ignored.
- Fix catch a polymorphic type by value
We now compile with GCC 8!
Change-Id: Iab70ce11190eee67608fc25c0bedff170152b153
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/11949
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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Otherwise the Linux kernel v4.17 boot fails with error:
Tried to write Gic cpu at offset 0xd0
Change-Id: Ie8063212c9e2b29e2e4766801b4b9538e9eccbf8
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11590
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The platform code uses a custom mechanism to traverse the object
hierarchy when generating device trees. This is highly undesirable
since this breaks for common cases such as when SimObjects are stored
in a list.
Change-Id: I1b968e5fa1db62f1456e3c0ac3de47ab1299e58d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10781
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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Previously, many devices were incorrecty configured to respond to an
address range of size 0xfff. This changes fixes this and sets it to
0x1000.
Change-Id: I4b027a27adf60ceae4859e287d7f34443b398752
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11116
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Add a new VExpress_GEM5_V1_Base Platform which configures basic on
chip devices. The original VExpress_GEM5_V1 will inherit the Base and
add more on chip devices (currently only the HDLCD). This change will
make it possible to create variations of the base platform with
different devices.
Change-Id: I21f9bf4f6217d87e811ff777f630122593eef013
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10807
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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Change-Id: I4c5203b216387d9a4f041c7a00caea926e5cfca6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10810
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This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Add an ARM-specific VirtIO MMIO device to the VExpress_GEM5_V1
platform.
Change-Id: Id1e75398e039aad9d637f46f653cda9084d3d2fe
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2327
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The MMIO interface currently only supports a subset of version 0.9.5
of the VirtIO specification. It has the following known limitations:
* The queue size hint (the QUEUE_NUM register) is ignored.
* Queue alignment is assumed to be hard-coded to
VirtQueue::ALIGN_SIZE (4096 bytes).
* Only 4096 byte pages are currently supported.
Change-Id: Ifd318f5e5bddab0b6a42d8c8af9ff2fbb477f98b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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Add GIC-based interrupt adaptor implementations that support PPI
(ArmPPI) and SPI (ArmSPI) delivery. In addition to being useful for
"normal" memory-mapped devices, the PPI adaptor makes it possible to
use the same device model to generate both PPIs and SPIs (e.g., the
PMU).
Change-Id: I73d6591c168040faef2443430c4f1da10c387a2a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2521
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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Change-Id: I1a4849283f9bd5b1856e1378f7cefc33fc14eebd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10023
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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When running gem5, the simulator outputs the following message to
describe the ports used by the VNC server and ther terminal:
Listening for system connection on port 5900
Listening for system connection on port 3456
The code used to extract the basename ('terminal' or 'vncserver') and
print that instead of system. However, this doesn't seem to work any
more. Change the code to output the full object name instead.
Change-Id: Ib27f66a5f8ba64c7a875b4e2f26a2e2ff48db8f3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10026
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Add a simple memory-mapped device that forwards writes to a serial
devices and treats reads as reads from the device. Unlike real UART
models, this one doesn't support interrupts.
This is useful to implement various debug devices that exist in many
systems.
Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10025
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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With this patch a gem5 System will store more info about its Masters.
While it was previously keeping track of the Master name and Master ID
only, it is now adding a per-Master pointer to the SimObject related to
the Master.
This will make it possible for a client to query a System for a Master
using either the master's name or the master's pointer.
Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9781
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Add support for TX interrupts and cleanup existing RX interrupt
handling.
Change-Id: If2e5b0c0cc6fbeb2dce09e7e9d935647516b2c47
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9769
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Move ps2.hh to dev/ps2/types.hh and update the device models to
consistently use well-known constants from this header.
Change-Id: Iadfdc774495957beb82f3d341107b1e9232ffd4c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9770
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The Pl050 KMI model currently has its own keyboard and mouse
models. Use the generic PS/2 interface instead.
Change-Id: I6523d26f8e38bcc8ba399d4d1a131723645d36c7
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9767
Reviewed-by: Gabe Black <gabeblack@google.com>
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The touchscreen model used ad-hoc mechanisms to enable/disable the
device. Use standard PS/2 commands to activate/deactivate the
device. Add proper TouchKit command handling.
Change-Id: I0c5a2e2b47639f36ab3ee07e3e559f11afa54b9d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9768
Reviewed-by: Gabe Black <gabeblack@google.com>
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