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2010-11-08ARM: Add checkpointing supportAli Saidi
2010-11-08ARM: Keep the warnings to a minimum.Ali Saidi
These warnings still need to be addresses, but pages of them is counterproductive.
2010-11-08Bus: Have the I/O devices that return address ranges print them out.Ali Saidi
This way we actually get device names associated with the devices.
2010-11-08sim: Use forward declarations for ports.Ali Saidi
Virtual ports need TLB data which means anything touching a file in the arch directory rebuilds any file that includes system.hh which in everything.
2010-10-17MIPS: Get rid of the backdoor device copy/pasted from and only used in Alpha.Gabe Black
2010-10-09UART: Make the 8250's MCR return a deterministic value.Gabe Black
This change makes the 8250 device return the value it has for the MCR when read instead of leaving the packet data unmodified/uninitialized. The value the UART has for the MCR may not be right, but that's a seperate issue that apparently hasn't caused any problems to date.
2010-10-01ARM: Add a fake flash controller so that unmodified linux can bootAli Saidi
With this change an unmodified Linux kernel can boot in M5.
2010-10-01ARM: Fix some subtle bugs in the GICPrakash Ramrakhyani
The GIC code can write to the registers with 8, 16, or 32 byte accesses which could set/clear different numbers of interrupts.
2010-09-16devices: undo cset 017baf09599f that added timer drain functions.Steve Reinhardt
It's not the right fix for the checkpoint deadlock problem Brad was having, and creates another bug where the system can deadlock on restore. Brad can't reproduce the original bug right now, so we'll wait until it arises again and then try to fix it the right way then.
2010-09-10style: fix sorting of includes and whitespace in some filesNathan Binkert
2010-08-23Devices: Allow a device to specify that a request is uncachable.Gene Wu
2010-08-23ARM: Change how the AMBA device ID checking is done to make it more genericAli Saidi
2010-08-23ARM: Add I/O devices for booting linuxAli Saidi
--HG-- rename : src/dev/arm/Versatile.py => src/dev/arm/RealView.py rename : src/dev/arm/versatile.cc => src/dev/arm/realview.cc rename : src/dev/arm/versatile.hh => src/dev/arm/realview.hh
2010-08-20devices: Fixed periodic interrupts to work with drainingBrad Beckmann
Added drain functions to the RTC and 8254 timer so that periodic interrupts stop when the system is draining. This patch is needed to checkpoint in timing mode. Otherwise under certain situations, the event queue will never be completely empty.
2010-08-17bus: clean up default responder code.Steve Reinhardt
Clean up some minor things left over from the default responder change in rev 9af6fb59752f. Mostly renaming the 'responder_set' param to 'use_default_range' to actually reflect what it does... old name wasn't that descriptive in the first place, but now it really doesn't make sense at all. Also got rid of the bogus obsolete assignment to 'bus.responder' which used to be a parameter but now is interpreted as an implicit child assignment, and which was giving me problems in the config restructuring to come. (A good argument for not allowing implicit child assignments, IMO, but that's water under the bridge, I'm afraid.) Also moved the Bus constructor to the .cc file since that's where it should have been all along.
2010-06-15stats: only consider a formula initialized if there is a formulaNathan Binkert
2010-06-03Act like enabling CPUs is no big deal,Steve Reinhardt
rather than a scary thing that might not work.
2010-06-02DMA: Make DmaPort generic enough to be used other placesAli Saidi
2010-06-02ARM: Adjust some copyrightsAli Saidi
2010-04-15tick: rename Clock namespace to SimClockNathan Binkert
2010-02-28uart: use integer versions of time instead of messing around with floatsNathan Binkert
2009-12-19X86: Add a latency that describes how long an interrupt takes to propagate ↵Gabe Black
through the IO APIC.
2009-11-18m5: removed master and slave deletions.Brad Beckmann
The unresolved destructor call caused a seg fault when called.
2009-11-18m5: fixed destructor to deschedule the tickEvent and eventBrad Beckmann
2009-11-17ARM: Boilerplate full-system code.Ali Saidi
--HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
2009-11-04build: fix compile problems pointed out by gcc 4.4Nathan Binkert
2009-10-15fixed MC146818 checkpointing bug and added isa serialization calls to ↵Brad Beckmann
simple_thread
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-08-20RTC: Make calls to writeData update the RTCs internal representation of time.Gabe Black
2009-08-20X86: Make the real time clock actually keep track of time.Gabe Black
2009-08-20X86: Don't insist on binary encoding for the RTC since we implement BCD.Gabe Black
2009-08-17X86: Move the simulated date in X86_FS forward to 2012.Gabe Black
2009-08-02X86: Set up the IDE device correctly, ie. with and using legacy ports.Gabe Black
2009-08-02IDE: Configure the IDE control to reflect the initial value of the command ↵Gabe Black
register.
2009-07-21MIPS: Get MIPS_FS to compile, more style fixes.Gabe Black
Some breakage was from my BitUnion change, some was much older.
2009-07-02typo: correct spellingNathan Binkert
2009-06-05types: need typename keyword to get the type.Nathan Binkert
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2009-05-20igbe: Fix descriptor cache bug.Steve Reinhardt
2009-05-17includes: sort includes againNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
--HG-- rename : src/sim/host.hh => src/base/types.hh
2009-04-26X86: Implement lowest priority interrupts more correctly.Gabe Black
Lowest priority interrupts are now delivered based on a rotating offset into the list of potential recipients. There could be parasitic cases were a processor gets picked on and ends up at that rotating offset all the time, but it's much more likely that the group will stay consistent and the pain will be distributed evenly.
2009-04-26X86: Tell the function that sends int messages who to send to instead of ↵Gabe Black
figuring it out itself.
2009-04-26X86: Make the local APICs register themselves with the IO APIC.Gabe Black
This is a hack so that the IO APIC can figure out information about the local APICs. The local APICs still have no way to find out about each other. Ideally, when the local APICs update state that's relevant to somebody else, they'd send an update to everyone. Without being able to do a broadcast, that would still require knowing who else there is to notify. Other broadcasts are implemented using assumptions that may not always be true.
2009-04-26X86: Record the initial APIC ID which identifies an APIC in M5.Gabe Black
The ID as exposed to software can be changed. Tracking those changes in M5 would be cumbersome, especially since there's no guarantee the IDs will remain unique.
2009-04-26X86, Config: Make makeX86System consider the number of CPUs, and clean up ↵Gabe Black
interrupt assignment.
2009-04-22i8254xGBe: major style overhaul.Steve Reinhardt
Moved DescCache template functions from .hh to .cc file. Also fixed lots of line-wrapping problems, and some irregular indentation.
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus.
2009-04-19X86: Mask the PIC at startup to avoid a glitch which causes an NMI.Gabe Black
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