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2007-10-07X86: Make an x86 platform object.Gabe Black
--HG-- extra : convert_revision : 7d64d3e78960f3bb937579f5d10937bed5f197be
2007-10-01CPU: fix sparc_fs booting with SimpleTimingCPU.Ali Saidi
--HG-- extra : convert_revision : 3d95f6daa7f0e8e376d1a880f64c056619263885
2007-09-28Rename cycles() function to ticks()Ali Saidi
--HG-- extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
2007-09-24X86: Get X86_FS to compile.Gabe Black
--HG-- extra : convert_revision : fb973bcf13648876d5691231845dd47a2be50f01
2007-09-12Devices: More fixes to Intel NIC Model.Ali Saidi
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2007-08-30Fix miscellaneous small typos.Miles Kaufmann
--HG-- extra : convert_revision : bfc0ac8e1c8a5d01d9fa5203184bbf99c8361da3
2007-08-30devices: Avoid using assert() to catch misconfigurationMiles Kaufmann
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2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) --HG-- extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
2007-08-26Merge with headGabe Black
--HG-- extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
2007-08-16PCI: Move PCI Configuration data into devices now that we can inherit ↵Ali Saidi
parameters. --HG-- extra : convert_revision : bd2214b28fb46a9a9e9e204e0539be33acb548ad
2007-08-16Devices: Make EtherInts connect in the same way memory ports currently do.Ali Saidi
--HG-- extra : convert_revision : 765b096785a77df9adc4791c9101b90696bd7be2
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
way so a cache can handle partial block requests for i/o devices. --HG-- extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
--HG-- extra : convert_revision : e06a950964286604274fba81dcca362d75847233
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-14Merge of DPRINTF fixes from head.Steve Reinhardt
--HG-- extra : convert_revision : f99a33b2df6a6c5592856d17d00e73ee83267442
2007-07-14Fix & tweak DPRINTFs for tracediff w/new cache code.Steve Reinhardt
Note that we should *not* print pointer values in DPRINTFs as these needlessly clutter tracediff output. --HG-- extra : convert_revision : 25a448f1b3ac8d453a717a104ad6dc0112fb30bb
2007-06-30Can only call makeAtomicResponse() once...Steve Reinhardt
--HG-- extra : convert_revision : c49aade46aa64f979da35eb653b544ee5bd82f01
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
(they function as adjectives not nouns) --HG-- extra : convert_revision : 6506474ff3356ae8c80ed276c3608d8a4680bfdb
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
now encoded in cmd field. --HG-- extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
2007-06-20Make sure all parameters have default values if they'reNathan Binkert
supposed to and make sure parameters have the right type. Also make sure that any object that should be an intermediate type has the right options set. --HG-- extra : convert_revision : d56910628d9a067699827adbc0a26ab629d11e93
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
--HG-- extra : convert_revision : 832e52ba80cbab2f5bb6d5b5977a499d41b4d638
2007-05-20Add new EventWrapper constructor that takes a Tick valueSteve Reinhardt
and schedules the event immediately. --HG-- extra : convert_revision : a84e729a5ef3632cbe6cff858c453c782707d983
2007-05-14couple more bug fixes for intel nicAli Saidi
src/dev/i8254xGBe.cc: src/dev/i8254xGBe.hh: couple more bug fixes --HG-- extra : convert_revision : ae5b806528c1ec06f0091e1f6e50fc0721057ddb
2007-05-14add uglyiness to fix dmasAli Saidi
src/dev/io_device.cc: extra printing and assertions src/mem/bridge.hh: deal with packets only satisfying part of a request by making many requests src/mem/cache/cache_impl.hh: make the cache try to satisfy a functional request from the cache above it before checking itself --HG-- extra : convert_revision : 1df52ab61d7967e14cc377c560495430a6af266a
2007-05-09couple of updates in the intel nicAli Saidi
--HG-- extra : convert_revision : da68e5e6411000d9d5247f769ee528a443286c61
2007-05-09update for new reschedule semanticsAli Saidi
--HG-- extra : convert_revision : 8c18b2513d638f67cc096e7f1483b47390a374ca
2007-05-09add a backoff algorithm when nacks are received by devicesAli Saidi
add seperate response buffers and request queue sizes in bus bridge add delay to respond to a nack in the bus bridge src/dev/i8254xGBe.cc: src/dev/ide_ctrl.cc: src/dev/ns_gige.cc: src/dev/pcidev.hh: src/dev/sinic.cc: add backoff delay parameters src/dev/io_device.cc: src/dev/io_device.hh: add a backoff algorithm when nacks are received. src/mem/bridge.cc: src/mem/bridge.hh: add seperate response buffers and request queue sizes add a new parameters to specify how long before a nack in ready to go after a packet that needs to be nacked is received src/mem/cache/cache_impl.hh: assert on the src/mem/tport.cc: add a friendly assert to make sure the packet was inserted into the list --HG-- extra : convert_revision : 3595ad932015a4ce2bb72772da7850ad91bd09b1
2007-05-01initialize lastTxInt to 0Ali Saidi
--HG-- extra : convert_revision : 4c5e9c2145b12fdeba91f3fdd8963c35abe326c2
2007-04-30fix igbe bugAli Saidi
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2007-04-30fix console printing bugAli Saidi
--HG-- extra : convert_revision : 5481b72b22e7a2cf3367d777309bc30201f3b1fc
2007-04-30add the ability for the ethernet device to check if the link is busyAli Saidi
--HG-- extra : convert_revision : 0dc0c4c4546869261f4508ad22a6a85aecf3c334
2007-04-21fixes for solaris compileAli Saidi
--HG-- extra : convert_revision : c82a62a61650e3700d237da917c453e5a9676320
2007-03-29make serialization at least seem to workAli Saidi
--HG-- extra : convert_revision : cbfdb64f9a204670b8dd0294c74a17044b9f330c
2007-03-27some more fixes... non-tso stuff seems to workAli Saidi
--HG-- extra : convert_revision : da604d20443376d04826397d0aaff0bdd744053b
2007-03-26first bit of life from the intel gigabit modelAli Saidi
--HG-- extra : convert_revision : d8944a53f6b585df21651c4e624518d5c49a7837
2007-03-22finish up the coding of the Intel Gb NIC... Many Many bugs to squashAli Saidi
src/dev/i8254xGBe.cc: src/dev/i8254xGBe.hh: src/dev/i8254xGBe_defs.hh: finish coding the Intel Gb NIC device src/dev/io_device.hh: we really don't want to be able to pass a null buffer to dma read, at least not the way we have things setup now... it won't work at all --HG-- extra : convert_revision : 6739497232317ec407cfa7a96de4575a9a6cfc46
2007-03-15add all the registers we'll need to support for the Intel GbE device and ↵Ali Saidi
support enough functionality make the driver think the device is there, and in good working order. src/dev/SConscript: add intel gbe to the dev SCons file src/dev/i8254xGBe.cc: src/dev/i8254xGBe.hh: src/dev/i8254xGBe_defs.hh: use new manner of registers and implement all device registers that are touched through boot and ifup --HG-- extra : convert_revision : b1a1767f0fd31cd371e432cb48ac9a2e9f9291b5
2007-03-13fix interrupting during a quisce on sparcAli Saidi
src/arch/sparc/ua2005.cc: fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to check if were suspended and interrupt at the guess time src/base/traceflags.py: add trace flag for Iob src/cpu/simple/base.cc: Use Quisce instead of IPI trace flag src/dev/sparc/iob.cc: add some Dprintfs --HG-- extra : convert_revision : 72e18fcc750ad1e4b2bb67b19b354eaffc6af6d5
2007-03-10Rework the way SCons recurses into subdirectories, making itNathan Binkert
automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. --HG-- extra : convert_revision : 103f6b490d2eb224436688c89cdc015211c4fd30
2007-03-10Compilation fixGabe Black
--HG-- extra : convert_revision : 8bfa5e9408d1ead0197aab5078c248876f90ea7a
2007-03-09implement ipi stufff for SPARCAli Saidi
src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/arch/x86/utility.hh: add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi src/arch/sparc/isa/decoder.isa: handle writable bits of strandstatus register in miscregfile src/arch/sparc/miscregfile.hh: some constants for the strand status register src/arch/sparc/ua2005.cc: properly implement the strand status register src/dev/sparc/iob.cc: implement ipi generation properly src/sim/system.cc: call into the ISA to start the CPU (or not) --HG-- extra : convert_revision : 0003b2032337d8a031a9fc044da726dbb2a9e36f
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. --HG-- extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
2007-03-03add a sparc fs regressionAli Saidi
src/dev/sparc/iob.cc: don't warn on cpu restart/idle/halt stuff tests/SConscript: add sparc target in test Sconscript util/regress: Add SPARC_FS target in regress --HG-- extra : convert_revision : 37fa21700ec4c350d87ca9723bc3359feb81c50a
2007-03-03Add Iob and remove the fake deviceAli Saidi
configs/common/FSConfig.py: add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy --HG-- extra : convert_revision : cf79a9a00760b7daf28063f407a04bd38b956843
2007-03-03Implement Niagara I/O interface and rework interruptsAli Saidi
configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore --HG-- extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
2007-02-21Get rid of the ConsoleListener SimObject and just fold theNathan Binkert
relevant code directly into the SimConsole object. Now, you can easily turn off the listen port by just specifying 0 as the port. --HG-- extra : convert_revision : c8937fa45b429d8a0728e6c720a599e38972aaf0
2007-02-21Make sure that all variables in the NSGigE device model areNathan Binkert
initialized. --HG-- extra : convert_revision : b4b156ed8e3c0c4c4f8043ff86dc232ebad38668
2007-02-13Make mulitple consoles work and be distinguishable from each otherAli Saidi
src/dev/alpha/tsunamireg.h: get rid of things that aren't really tsunami registers src/dev/platform.hh: src/dev/uart.cc: the uart pointer isn't used anymore src/dev/simconsole.cc: make the simconsole print something more useful to distinguish between various consoles in a single system src/dev/uart8250.hh: put the needed uart defines in here rather than including them from tsunamireg src/python/m5/objects/T1000.py: add a console to the T1000 config for the hypervisor --HG-- extra : convert_revision : 76ca92122e611eaf76b989bc699582eef8297be8
2007-02-07Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head --HG-- extra : convert_revision : c56b8160b403fde235636ca5b5b4cecd206ffa4c
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 06:13:38 +0000