gem5 - gem5

Age	Commit message (Expand)	Author
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-07-09	Fix: Address a few benign memory leaks	Andreas Hansson
2012-06-27	ARM: Fix address range issue with VExpress EMM	Ali Saidi
2012-06-05	ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELT	Geoffrey Blake
2012-06-05	ARM: PS2 encoding fix	Chander Sudanthi
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-06-05	ARM: Fix over-eager assert in gic.	Ali Saidi
2012-05-23	DMA: Split the DMA device and IO device into seperate files	Andreas Hansson
2012-05-23	MEM: Add a snooping DMA port subclass for table walker	Andreas Hansson
2012-05-10	ARM: fix the calculation of the values in the RV clocks	Koan-Sin Tan
2012-05-10	ARM: pl011 raw interrupt fix	Chander Sudanthi
2012-05-10	ARM: EMM board address range fix	Chander Sudanthi
2012-05-10	dev: use correct delete operation in SimpleDisk	Ali Saidi
2012-05-10	ARM: Fix incorrect use of not operators in arm devices	Ali Saidi
2012-05-10	gem5: assert before indexing intro arrays to verify bounds	Ali Saidi
2012-05-10	gem5: Fix a number of incorrect case statements	Ali Saidi
2012-05-10	IGbE: Fix writeback conditions for i8254x GbE in updated data sheet.	Pritha Ghoshal
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-04-05	Config: corrects the way Ruby attaches to the DMA ports	Nilay Vaish
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
2012-03-21	ARM: Add RTC to PBX System	Koan-Sin Tan
2012-03-21	ARM: Fix uninitialized value in ARM RTC model.	Ali Saidi
2012-03-19	gcc: Clean-up of non-C++0x compliant code, first steps	Andreas Hansson
2012-03-01	ARM: FIx missing cf controller connection.	Ali Saidi
2012-03-01	ARM: Add support for Versatile Express extended memory map	Ali Saidi
2012-03-01	ARM: Add RTC device for ARM platforms.	Ali Saidi
2012-02-24	MEM: Prepare mport for master/slave split	Andreas Hansson
2012-02-24	MEM: Move all read/write blob functions from Port to PortProxy	Andreas Hansson
2012-02-24	MEM: Make port proxies use references rather than pointers	Andreas Hansson
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
2012-02-14	MEM: Fix residual bus ports and make them master/slave	Andreas Hansson
2012-02-13	MEM: Explicit ports and Python binding on CopyEngine	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-02-01	configs: More fixes for the memory system updates	Ali Saidi
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-29	Implement Ali's review feedback.	Gabe Black
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-27	ns_gige: Fix a missing curly brace in if-statement	Andreas Hansson
2012-01-16	Merge yet again with the main repository.	Gabe Black
2012-01-17	MEM: Removing the default port peer from Python ports	Andreas Hansson
2012-01-17	MEM: Make the bus bridge unidirectional and fixed address range	Andreas Hansson
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	MEM: Simplify ports by removing EventManager	Andreas Hansson