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2016-05-19arm,dev: PL011 UART_FR read status enhancementBjoern A. Zeeb
Given we do not simulate a FIFO currently there are only two states we can be in upon read: empty or full. Properly signal the latter. Add and sort constants for states in the header file. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19dev, virtio: properly set PCI address space to use IOREGBjoern A. Zeeb
VirtIO spec < 1.0 demands IOREG to be used on PCI and not memory mapped. Set the correct bit on the PCI address accordingly. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-06dev, arm: Update GIC to use GICv2 register namingAndreas Sandberg
The GICv2 has a new and slightly more consistent register naming. Update gem5's GIC register names to match the new documentation. Change-Id: I8ef114eee8a95bf0b88b37c18a18e137be78675a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-04-27dev: Fix incorrect terminal backlog handlingAndreas Sandberg
The Terminal device currently uses the peek functionality in gem5's circular buffer implementation to send existing buffered content on the terminal when a new client attaches. This functionallity is however not implemented correctly and re-sends the same block multiple time. Add the required functionality to peek with an offset into the circular buffer and change the Terminal::accept() implementation to send the buffered contents. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-12misc: Appease clang...againAndreas Hansson
Once again, clang is having issues with recently committed code. Unfortunately HSAIL_X86 is still broken.
2016-04-07Revert to 74c1e6513bd0 (sim: Thermal support for Linux)Andreas Sandberg
2014-11-18power: Add power states to ClockedObjectAkash Bagdia
Add 4 power states to the ClockedObject, provides necessary access functions to check and update the power state. Default power state is UNDEFINED, it is responsibility of the respective simulation model to provide the startup state and any other logic for state change. Add number of transition stat. Add distribution of time spent in clock gated state. Add power state residency stat. Add dump call back function to allow stats update of distribution and residency stats.
2015-05-13sim: Thermal support for LinuxDavid Guillen Fandos
This patch enables Linux to read the temperature using hwmon infrastructure. In order to use this in your gem5 you need to compile the kernel using the following configs: CONFIG_HWMON=y CONFIG_SENSORS_VEXPRESS=y And a proper dts file (containing an entry such as): dcc { compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; temp@0 { compatible = "arm,vexpress-temp"; arm,vexpress-sysreg,func = <4 0>; label = "DCC"; }; };
2015-11-26dev: Add post-fork handling for disk imagesAndreas Sandberg
This changeset adds support for notifying the disk images that the simulator has been forked. We need to disable the saving of the CoW disk image from the child process, and we need to make sure that systems which use a raw disk image are not allowed to fork to avoid two or more gem5 processes writing to the same disk image. Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se> [sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version] Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2015-11-27base: Add support for changing output directoriesAndreas Sandberg
This changeset adds support for changing the simulator output directory. This can be useful when the simulation goes through several stages (e.g., a warming phase, a simulation phase, and a verification phase) since it allows the output from each stage to be located in a different directory. Relocation is done by calling core.setOutputDir() from Python or simout.setOutputDirectory() from C++. This change affects several parts of the design of the gem5's output subsystem. First, files returned by an OutputDirectory instance (e.g., simout) are of the type OutputStream instead of a std::ostream. This allows us to do some more book keeping and control re-opening of files when the output directory is changed. Second, new subdirectories are OutputDirectory instances, which should be used to create files in that sub-directory. Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se> [sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version] Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-02-23dev, arm: Implement the NoMali reset callbackAndreas Sandberg
Add a callback handler for the NoMali reset callback. This callback is called whenever the GPU is reset using the register interface or the NoMali API. The callback can be used to override ID registers using the raw register API.
2016-02-23dev, arm: Refactor the NoMali GPUAndreas Sandberg
Refactor and cleanup the NoMaliGpu class: * Use a std::map instead of a switch block to map the parameter enum describing the GPU type to a NoMali type. * Remove redundant NoMali handle from the interrupt callback. * Make callbacks and API wrappers protected instead of private to enable future extensions. * Wrap remaining NoMali API calls.
2016-02-23scons: Add missing override to appease clangAndreas Hansson
Make clang happy...again.
2016-02-15misc: Add missing overrides to appease clangAndreas Hansson
Since the last round of fixes a few new issues have snuck in. We should consider switching the regression runs to clang.
2016-02-06style: eliminate explicit boolean comparisonsSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-control -a' to get rid of '== true' comparisons, plus trivial manual edits to get rid of '== false'/'== False' comparisons. Left a couple of explicit comparisons in where they didn't seem unreasonable: invalid boolean comparison in src/arch/mips/interrupts.cc:155 >> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<< invalid boolean comparison in src/unittest/unittest.hh:110 >> "EXPECT_FALSE(" #expr ")", (expr) == false)<<
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-control -a'.
2016-02-06style: remove trailing whitespaceSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-white -a'.
2016-02-06dist, dev: add an ethernet switch modelMohammad Alian
2016-01-17sim: don't ignore SIG_TRAPSteve Reinhardt
By ignoring SIG_TRAP, using --debug-break <N> when not connected to a debugger becomes a no-op. Apparently this was intended to be a feature, though the rationale is not clear. If we don't ignore SIG_TRAP, then using --debug-break <N> when not connected to a debugger causes the simulation process to terminate at tick N. This is occasionally useful, e.g., if you just want to collect a trace for a specific window of execution then you can combine this with --debug-start to do exactly that. In addition to not ignoring the signal, this patch also updates the --debug-break help message and deletes a handful of unprotected calls to Debug::breakpoint() that relied on the prior behavior.
2016-01-15dev, arm: Add a platform with support for both aarch32 and aarch64Andreas Sandberg
Add a platform with support for both aarch32 and aarch64. This platform implements a subset of the devices in a real Versatile Express and extends it with some gem5-specific functionality. It is in many ways similar to the old VExpress_EMM64 platform, but supports the following new features: * Automatic PCI interrupt assignment * PCI interrupts allocated in a contiguous range. * Automatic boot loader selection (32-bit / 64-bit) * Cleaner memory map where gem5-specific devices live in CS5 which isn't used by current Versatile Express platforms. * No fake devices. Devices that were previously faked will be removed from the device tree instead. * Support for 510 GiB contiguous memory
2016-01-15dev, arm: Add support for automatic PCI interrupt routingAndreas Sandberg
Add support for automatic PCI interrupt routing using a device's ID on the PCI bus. Our current DTBs typically tell the kernel that we do this or something similar when declaring the PCI controller. This changeset adds an option to make the simulator behave in the same way. Interrupt routing can be selected by setting the int_policy parameter in the GenericArmPciHost. The following values are supported: * ARM_PCI_INT_STATIC: Use the old static routing policy using the interrupt line from a device's configurtion space. * ARM_PCI_INT_DEV: Use device number on the PCI bus to map to an interrupt in the GIC. The interrupt is computed as: gic_int = int_base + (pci_dev % int_count) * ARM_PCI_INT_PIN: Use device interrupt pin on the PCI bus to map to an interrupt in the GIC. The PCI specification reserves pin ID 0 for devices without interrupts, the interrupt therefore computed as: gic_int = int_base + ((pin - 1) % int_count)
2016-01-11scons: Enable -Wextra by defaultAndreas Hansson
Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial.
2016-01-07dev: Distributed Ethernet link for distributed gem5 simulationsGabor Dozsa
Distributed gem5 (abbreviated dist-gem5) is the result of the convergence effort between multi-gem5 and pd-gem5 (from Univ. of Wisconsin). It relies on the base multi-gem5 infrastructure for packet forwarding, synchronisation and checkpointing but combines those with the elaborated network switch model from pd-gem5. --HG-- rename : src/dev/net/multi_etherlink.cc => src/dev/net/dist_etherlink.cc rename : src/dev/net/multi_etherlink.hh => src/dev/net/dist_etherlink.hh rename : src/dev/net/multi_iface.cc => src/dev/net/dist_iface.cc rename : src/dev/net/multi_iface.hh => src/dev/net/dist_iface.hh rename : src/dev/net/multi_packet.hh => src/dev/net/dist_packet.hh
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
This patch changes the name of a bunch of packet flags and MSHR member functions and variables to make the coherency protocol easier to understand. In addition the patch adds and updates lots of descriptions, explicitly spelling out assumptions. The following name changes are made: * the packet memInhibit flag is renamed to cacheResponding * the packet sharedAsserted flag is renamed to hasSharers * the packet NeedsExclusive attribute is renamed to NeedsWritable * the packet isSupplyExclusive is renamed responderHadWritable * the MSHR pendingDirty is renamed to pendingModified The cache states, Modified, Owned, Exclusive, Shared are also called out in the cache and MSHR code to make it easier to understand.
2015-12-10dev: Add missing SConscript in src/dev/i2cAndreas Sandberg
2015-12-10dev: Move storage devices to src/dev/storage/Andreas Sandberg
Move the IDE controller and the disk implementations to src/dev/storage. --HG-- rename : src/dev/DiskImage.py => src/dev/storage/DiskImage.py rename : src/dev/Ide.py => src/dev/storage/Ide.py rename : src/dev/SimpleDisk.py => src/dev/storage/SimpleDisk.py rename : src/dev/disk_image.cc => src/dev/storage/disk_image.cc rename : src/dev/disk_image.hh => src/dev/storage/disk_image.hh rename : src/dev/ide_atareg.h => src/dev/storage/ide_atareg.h rename : src/dev/ide_ctrl.cc => src/dev/storage/ide_ctrl.cc rename : src/dev/ide_ctrl.hh => src/dev/storage/ide_ctrl.hh rename : src/dev/ide_disk.cc => src/dev/storage/ide_disk.cc rename : src/dev/ide_disk.hh => src/dev/storage/ide_disk.hh rename : src/dev/ide_wdcreg.h => src/dev/storage/ide_wdcreg.h rename : src/dev/simple_disk.cc => src/dev/storage/simple_disk.cc rename : src/dev/simple_disk.hh => src/dev/storage/simple_disk.hh
2015-12-10dev: Move network devices to src/dev/net/Andreas Sandberg
--HG-- rename : src/dev/Ethernet.py => src/dev/net/Ethernet.py rename : src/dev/etherbus.cc => src/dev/net/etherbus.cc rename : src/dev/etherbus.hh => src/dev/net/etherbus.hh rename : src/dev/etherdevice.cc => src/dev/net/etherdevice.cc rename : src/dev/etherdevice.hh => src/dev/net/etherdevice.hh rename : src/dev/etherdump.cc => src/dev/net/etherdump.cc rename : src/dev/etherdump.hh => src/dev/net/etherdump.hh rename : src/dev/etherint.cc => src/dev/net/etherint.cc rename : src/dev/etherint.hh => src/dev/net/etherint.hh rename : src/dev/etherlink.cc => src/dev/net/etherlink.cc rename : src/dev/etherlink.hh => src/dev/net/etherlink.hh rename : src/dev/etherobject.hh => src/dev/net/etherobject.hh rename : src/dev/etherpkt.cc => src/dev/net/etherpkt.cc rename : src/dev/etherpkt.hh => src/dev/net/etherpkt.hh rename : src/dev/ethertap.cc => src/dev/net/ethertap.cc rename : src/dev/ethertap.hh => src/dev/net/ethertap.hh rename : src/dev/i8254xGBe.cc => src/dev/net/i8254xGBe.cc rename : src/dev/i8254xGBe.hh => src/dev/net/i8254xGBe.hh rename : src/dev/i8254xGBe_defs.hh => src/dev/net/i8254xGBe_defs.hh rename : src/dev/multi_etherlink.cc => src/dev/net/multi_etherlink.cc rename : src/dev/multi_etherlink.hh => src/dev/net/multi_etherlink.hh rename : src/dev/multi_iface.cc => src/dev/net/multi_iface.cc rename : src/dev/multi_iface.hh => src/dev/net/multi_iface.hh rename : src/dev/multi_packet.cc => src/dev/net/multi_packet.cc rename : src/dev/multi_packet.hh => src/dev/net/multi_packet.hh rename : src/dev/ns_gige.cc => src/dev/net/ns_gige.cc rename : src/dev/ns_gige.hh => src/dev/net/ns_gige.hh rename : src/dev/ns_gige_reg.h => src/dev/net/ns_gige_reg.h rename : src/dev/pktfifo.cc => src/dev/net/pktfifo.cc rename : src/dev/pktfifo.hh => src/dev/net/pktfifo.hh rename : src/dev/sinic.cc => src/dev/net/sinic.cc rename : src/dev/sinic.hh => src/dev/net/sinic.hh rename : src/dev/sinicreg.hh => src/dev/net/sinicreg.hh rename : src/dev/tcp_iface.cc => src/dev/net/tcp_iface.cc rename : src/dev/tcp_iface.hh => src/dev/net/tcp_iface.hh
2015-12-10dev: Move i2c functionality to src/dev/i2c/Andreas Sandberg
--HG-- rename : src/dev/I2C.py => src/dev/i2c/I2C.py rename : src/dev/i2cbus.cc => src/dev/i2c/bus.cc rename : src/dev/i2cbus.hh => src/dev/i2c/bus.hh rename : src/dev/i2cdev.hh => src/dev/i2c/device.hh
2015-12-10dev: Move the CopyEngine class to src/dev/pciAndreas Sandberg
--HG-- rename : src/dev/CopyEngine.py => src/dev/pci/CopyEngine.py rename : src/dev/copy_engine.cc => src/dev/pci/copy_engine.cc rename : src/dev/copy_engine.hh => src/dev/pci/copy_engine.hh rename : src/dev/copy_engine_defs.hh => src/dev/pci/copy_engine_defs.hh
2015-12-10dev: Move existing PCI device functionality to src/dev/pciAndreas Sandberg
Move pcidev.(hh|cc) to src/dev/pci/device.(hh|cc) and update existing devices to use the new header location. This also renames the PCIDEV debug flag to have a capitalization that is consistent with the PCI host and other devices. --HG-- rename : src/dev/Pci.py => src/dev/pci/PciDevice.py rename : src/dev/pcidev.cc => src/dev/pci/device.cc rename : src/dev/pcidev.hh => src/dev/pci/device.hh rename : src/dev/pcireg.h => src/dev/pci/pcireg.h
2015-09-18dev, arm: Add gem5 extensions to support more than 8 coresKarthik Sangaiah
Previous ARM-based simulations were limited to 8 cores due to limitations in GICv2 and earlier. This changeset adds a set of gem5-specific extensions that enable support for up to 256 cores. When the gem5 extensions are enabled, the GIC uses CPU IDs instead of a CPU bitmask in the GIC's register interface. To OS can enable the extensions by setting bit 0x200 in ICDICTR. This changeset is based on previous work by Matt Evans.
2015-12-05dev: Rewrite PCI host functionalityAndreas Sandberg
The gem5's current PCI host functionality is very ad hoc. The current implementations require PCI devices to be hooked up to the configuration space via a separate configuration port. Devices query the platform to get their config-space address range. Un-mapped parts of the config space are intercepted using the XBar's default port mechanism and a magic catch-all device (PciConfigAll). This changeset redesigns the PCI host functionality to improve code reuse and make config-space and interrupt mapping more transparent. Existing platform code has been updated to use the new PCI host and configured to stay backwards compatible (i.e., no guest-side visible changes). The current implementation does not expose any new functionality, but it can easily be extended with features such as automatic interrupt mapping. PCI devices now register themselves with a PCI host controller. The host controller interface is defined in the abstract base class PciHost. Registration is done by PciHost::registerDevice() which takes the device, its bus position (bus/dev/func tuple), and its interrupt pin (INTA-INTC) as a parameter. The registration interface returns a PciHost::DeviceInterface that the PCI device can use to query memory mappings and signal interrupts. The host device manages the entire PCI configuration space. Accesses to devices decoded into the devices bus position and then forwarded to the correct device. Basic PCI host functionality is implemented in the GenericPciHost base class. Most platforms can use this class as a basic PCI controller. It provides the following functionality: * Configurable configuration space decoding. The number of bits dedicated to a device is a prameter, making it possible to support both CAM, ECAM, and legacy mappings. * Basic interrupt mapping using the interruptLine value from a device's configuration space. This behavior is the same as in the old implementation. More advanced controllers can override the interrupt mapping method to dynamically assign host interrupts to PCI devices. * Simple (base + addr) remapping from the PCI bus's address space to physical addresses for PIO, memory, and DMA.
2015-12-04dev, arm: Disable R/B swap in HDLCD by defaultAndreas Sandberg
The HDLCD model implements a workaround that swaps the red and blue channels. This works around an issue in certain old kernels. The new driver doesn't seem to have this behavior, so disable the workaround by default and enable it in the affected platforms.
2015-12-04dev, arm: Split MCC and DCC subsystemsAndreas Sandberg
Devices behind the Versatile Express configuration controllers are currently all lumped into one SimObject. This will make DTB generation challenging since the DTB assumes them to be in different parts of the hierarchy. It also makes it hard to model other CoreTiles without also replicating devices from the motherboard. This changeset splits the VExpressCoreTileCtrl into two subsystems: VExpressMCC for all motherboard-related devices and CoreTile2A15DCC for Core Tile specific devices.
2015-12-03dev, mips: Remove the unused MaltaPChip classAndreas Sandberg
The MaltaPChip class is currently unused and identical (except for the class name) to the TsunamiPChip. If someone decides to implement PCI for Malta, they should make sure to share code with the Tsunami implementation if they are similar.
2015-11-24dev: Remove unnecessary header includeAndreas Sandberg
--HG-- extra : rebase_source : 64046371962e98413757bc3ab0c0d48dfb11ff1e
2015-11-22arm, dev: Fix flash model serialization code typosGeoffrey Blake
The flash model has typos in its serialization code for unknownPages, locationTable, blockValidEntries, and blockEmptyEntries arrays where it would save each entry in the array under the same name in the checkpoint. This patch fixes these typos.
2015-11-11dev, arm: Initialized the iccrpr register in the GICAndreas Sandberg
The IICRPR register in the GIC is currently not being initialized when the GIC is instantiated. Initialize to the value mandated by the architecture specification.
2015-11-05dev: Add basic checkpoint support to VirtIO9PProxy deviceSascha Bischoff
This patch adds very basic checkpoint support for the VirtIO9PProxy device. Previously, attempts to checkpoint gem5 with a present 9P device caused gem5 to fatal as none of the state is tracked. We still do not track any state, but we replace the fatal with a warning which is triggered if the device has been used by the guest system. In the event that it has not been used, we assume that no state is lost during checkpointing. The warning is triggered on both a serialize and an unserialize to ensure maximum visibility for the user.
2015-11-09dev: Remove unused header includesAndreas Sandberg
Devices should never need to include dev/pciconfall.hh. --HG-- extra : amend_source : 3a6e56485d432b49e2af22407982fa785c0ccb68
2015-11-09dev: Don't access the platform directly in PCI devicesAndreas Sandberg
Cleanup PCI devices to avoid using the PciDevice::platform pointer directly. The PCI-specific functionality provided by the Platform should be accessed through the wrappers in PciDevice.
2015-11-06mem: Use the packet delays and do not just zero them outAndreas Hansson
This patch updates the I/O devices, bridge and simple memory to take the packet header and payload delay into account in their latency calculations. In all cases we add the header delay, i.e. the accumulated pipeline delay of any crossbars, and the payload delay needed for deserialisation of any payload. Due to the additional unknown latency contribution, the packet queue of the simple memory is changed to use insertion sorting based on the time stamp. Moreover, since the memory hands out exclusive (non shared) responses, we also need to ensure ordering for reads to the same address.
2015-10-29dev: Fix segfault in flash deviceSascha Bischoff
Fix a bug in which the flash device would write out of bounds and could either trigger a segfault and corrupt the memory of other objects. This was caused by using pageSize in the place of pagesPerBlock when running the garbage collector. Also, added an assert to flag this condition in the future.
2015-10-29dev: Fix draining for UFSHostDevice and FlashDeviceSascha Bischoff
This patch fixes the drain logic for the UFSHostDevice and the FlashDevice. In the case of the FlashDevice, the logic for CheckDrain needed to be reversed, whilst in the case of the UFSHostDevice check drain was never being called. In both cases the system would never complete draining if the initial attampt to drain failed.
2015-10-23x86: Add missing explicit overrides for X86 devicesAndreas Hansson
Make clang >= 3.5 happy when compiling build/X86/gem5.opt on OSX.
2015-10-23arm: Add missing explicit overrides for ARM devicesAndreas Hansson
Make clang >= 3.5 happy when compiling build/ARM/gem5.opt on OSX.
2015-10-12misc: Add explicit overrides and fix other clang >= 3.5 issuesAndreas Hansson
This patch adds explicit overrides as this is now required when using "-Wall" with clang >= 3.5, the latter now part of the most recent XCode. The patch consequently removes "virtual" for those methods where "override" is added. The latter should be enough of an indication. As part of this patch, a few minor issues that clang >= 3.5 complains about are also resolved (unused methods and variables).
2015-10-12misc: Remove redundant compiler-specific definesAndreas Hansson
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions.
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
Adds per-thread interrupt controllers and thread/context logic so that interrupts properly get routed in SMT systems.
2015-09-29arch, x86: Delete packet in IntDevice::recvResponseJoel Hestness
IntDevice::recvResponse is called from two places in current mainline: (1) the short circuit path of X86ISA::IntDevice::IntMasterPort::sendMessage for atomic mode, and (2) the full request->response path to and from the x86 interrupts device (finally called from MessageMasterPort::recvTimingResp). In the former case, the packet was deleted correctly, but in the latter case, the packet and request leak. To fix the leak, move request and packet deletion into IntDevice inherited class implementations of recvResponse.