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AgeCommit message (Expand)Author
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-07-09Fix: Address a few benign memory leaksAndreas Hansson
2012-06-27ARM: Fix address range issue with VExpress EMMAli Saidi
2012-06-05ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELTGeoffrey Blake
2012-06-05ARM: PS2 encoding fixChander Sudanthi
2012-06-05sim: Remove FastAllocAli Saidi
2012-06-05ARM: Fix over-eager assert in gic.Ali Saidi
2012-05-23DMA: Split the DMA device and IO device into seperate filesAndreas Hansson
2012-05-23MEM: Add a snooping DMA port subclass for table walkerAndreas Hansson
2012-05-10ARM: fix the calculation of the values in the RV clocksKoan-Sin Tan
2012-05-10ARM: pl011 raw interrupt fixChander Sudanthi
2012-05-10ARM: EMM board address range fixChander Sudanthi
2012-05-10dev: use correct delete operation in SimpleDiskAli Saidi
2012-05-10ARM: Fix incorrect use of not operators in arm devicesAli Saidi
2012-05-10gem5: assert before indexing intro arrays to verify boundsAli Saidi
2012-05-10gem5: Fix a number of incorrect case statementsAli Saidi
2012-05-10IGbE: Fix writeback conditions for i8254x GbE in updated data sheet.Pritha Ghoshal
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-04-05Config: corrects the way Ruby attaches to the DMA portsNilay Vaish
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
2012-03-21ARM: Add RTC to PBX SystemKoan-Sin Tan
2012-03-21ARM: Fix uninitialized value in ARM RTC model.Ali Saidi
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-01ARM: FIx missing cf controller connection.Ali Saidi
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
2012-03-01ARM: Add RTC device for ARM platforms.Ali Saidi
2012-02-24MEM: Prepare mport for master/slave splitAndreas Hansson
2012-02-24MEM: Move all read/write blob functions from Port to PortProxyAndreas Hansson
2012-02-24MEM: Make port proxies use references rather than pointersAndreas Hansson
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-02-14MEM: Fix residual bus ports and make them master/slaveAndreas Hansson
2012-02-13MEM: Explicit ports and Python binding on CopyEngineAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-01configs: More fixes for the memory system updatesAli Saidi
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-29Implement Ali's review feedback.Gabe Black
2012-01-28Merge with the main repo.Gabe Black
2012-01-27ns_gige: Fix a missing curly brace in if-statementAndreas Hansson
2012-01-16Merge yet again with the main repository.Gabe Black
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Simplify ports by removing EventManagerAndreas Hansson