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Proposed changes to SPARC FS simulation, testing indicates that checkpoints are now loaded correctly with the following command: build/SPARC/gem5.opt configs/example/fs.py -r 1
Change-Id: Icd44f01a74c41a78828ef6fd7b661e584bdb6966
Reviewed-on: https://gem5-review.googlesource.com/8581
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Change-Id: I412d0b5edf2a08217792fa2ed1e511c17d3d31d4
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8141
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The patch that added M5_FALLTHROUGH (5c41076bd7610 misc: Updates for gcc7.2
for x86) incorrectly added breaks to the i8042 device without implementing
the correct functions. This patch implements keyboard writes, but ignores
output writes.
Information on the PS2 controller can be found at
https://wiki.osdev.org/%228042%22_PS/2_Controller
Note: Without this patch Linux 4.14 won't boot.
Change-Id: I7de137b46cef00e6c1f1c14335cb52107cd7fe5b
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/7301
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Enables automatic generation of Device Trees for RealView PCI host
controllers. Note that some parts are more hard coded than you'd want,
but this is due to the limited understanding the PCI host has of its
configuration (i.e. it doesn't know all memory ranges). Fixing this,
for now at least, went beyond the scope and intentions of the
Device Tree generating code: use with care!
Change-Id: I2041871e0eb4d04fb5191257c47dd38649d1c0cc
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5967
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Adds Device Tree methods for the energy controller to allow for
DVFS simulations with automatically generated DTB files
Change-Id: Id8682f07dff1bbe63987e757faa0694e03ee86ab
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5966
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Implements the Device Tree generating code for devices required by the
RealView VExpress_GEM5_V1 platform
Change-Id: I14244b2f3c028cbddba3c23ce7433fe3b301a0e8
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5965
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Equips cpu models with a method to generate the cpu node.
Note: even though official documentation requires that CPU ids start
counting from 0 in every cluster, GEM5 requires a globally unique cpu_id.
Change-Id: Ida3e17af3124a68ef7dbf2449cd034dfc3ec39df
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5963
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Within a device tree, the GenericTimer device needs to point (via phandle)
to a clock domain which is itself also an object in the device tree. Within
gem5, clock domains are managed by making all clocked SimObjects inherit
from ClockedObject rather than SimObject.
Without this change, the GenericTimer is unable to generate the appropriate
clock domain phandle, and will crash during DTB autogeneration.
Change-Id: I6d3fb6362847c6a01720b2f14b3d595d1e59f01f
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4960
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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They are now oriented around a class which makes it easy to provide
custom setter/getter functions which let you set or read bits in an
arbitrary way.
Future additions may add the ability to add custom bitfield methods,
and index-able bitfields.
Change-Id: Ibd6d4d9e49107490f6dad30a4379a8c93bda9333
Reviewed-on: https://gem5-review.googlesource.com/7201
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Several files in the repository were tracked with execute permissions
even though the files are just normal C/C++ files (and the one .isa).
Change-Id: I976b096acab4a1fc74c5699ef1f9b222c1e635c2
Reviewed-on: https://gem5-review.googlesource.com/7241
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:
* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878
Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>
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These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).
Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
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A recent serial device refactoring changed the name of the parameter
that the terminal device gets attached to on the UART. The x86 and
SPARC platform devices didn't get updated though, and were still using
the old name. This change updates those objects.
Reported-by: Kanad Basu <kanad.kut@gmail.com>
Change-Id: I0824a9df8639062d8561420ea9ffea26b8b7e2e9
Reviewed-on: https://gem5-review.googlesource.com/5781
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Recent Linux kernels for AArch64 have changed their start addresses
but we still want to relocate the kernel to 0x80080000 which
required hacking the load_addr_mask in Realview.py to be 0x7ffffff
from 0xfffffff to mask off the proper number of MSBs to load the
kernel in the desired location. To avoid having to make this change
in the future again, we auto-calculate the load_addr_mask if it is
specified as 0x0 in the System sim-object to find the most restrictive
address mask instead of having the configuration specify it. If the
configuration does specify the address mask, we use it instead of
auto-calculating.
Change-Id: I18aabb5d09945c6e3e3819c9c8036ea24b6c35cf
Signed-off-by: Geoffrey Blake <Geoffrey.Blake@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2323
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: I104227fc460f8b561e7375b329a541c1fce881b2
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4291
Reviewed-by: Gabe Black <gabeblack@google.com>
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Add a dummy serial device that discards any output and doesn't provide
any input. This device can be used to terminate UARTs that don't have
a default device (e.g., a terminal) attached.
Change-Id: I4a6b0b5037ce360f59bfb5c566e1698d113a1d26
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4290
Reviewed-by: Gabe Black <gabeblack@google.com>
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The UART models currently assume that they are always wired to a
terminal. While true at the moment, this isn't necessarily a valid
assumption. This change introduces the SerialDevice class that defines
the interface for serial devices. Currently, Terminal is the only
class that implements this interface.
Change-Id: I74fefafbbaf5ac1ec0d4ec0b5a0f4b246fdad305
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4289
Reviewed-by: Gabe Black <gabeblack@google.com>
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The fixed image writer (which was dumping .bmp images only) has been
replaced by the configurable one in HDLcd device. Default format is
Auto, which gives gem5 the freedom to choose the format it prefers.
Change-Id: I0643266556bb10b43cdebd628f6daa2cd5e105dd
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5183
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Originally it was possible to use a Bitmap writer class for dumping a
framebuffer snapshot in a .bmp file. This patch enables you to choose
another format. In particular it implements the writing of PNG Images
using libpng library. The latter has to be already installed in your
machine, otherwise gem5 will default to the Bitmap format. This
configurable writer has been introduced in the VNC frame dumping mechanism,
which is storing changed frame buffers from the VNC server
Change-Id: Id7e5763c82235f1ce90381c8486b85a7cce734ce
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5181
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Only panic if there are disks which would actually be connected to it beyond
its limit. Also skip past disks which are set to NULL. This is useful since
it lets you set up disks on different ports of the controller instead of
filling them contiguously.
Change-Id: I92f1316d3ad6931e25bfffeb34fb2603c0b95ce7
Reviewed-on: https://gem5-review.googlesource.com/4848
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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* When dispatching multiple gem5 simulations at once, they race
for the socket id, resulting in a panic when calling 'bind'. To
avoid this problem, the socket id is now created before the diod
process is created. In case of a race, a panic is called in the
gem5 process, whereas before the panic was called in the diod
process where it didn't have any effect.
* In some cases killing the diod process in terminateDiod() using
only SIGTERM failed, so a call using SIGKILL is added.
Change-Id: Ie10741e10af52c8d255210cd4bfe0e5d761485d3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2821
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The error message says an IDE controller can support at most 4 disks, but the
check would fail if there were more than 3 disks.
Change-Id: Ic7d5d8c941fe2580da43019f53991377d4727bb9
Reviewed-on: https://gem5-review.googlesource.com/4460
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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ISA devices typically run in the device event queue. Previously, we
assumed that devices would perform their own EQ migrations as
needed. This isn't ideal since it means we have different conventions
for IO devices and ISA devices. Switch to doing migrations in the KVM
CPU instead to make the behavior consistent.
Change-Id: I33b74480fb2126b0786dbdbfdcfa86083384250c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4288
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: Ic59add8afee1d49633634272d9687a4b1558537e
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3929
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I965d31ff8ad1658b03a902bf4244d7d0977b0466
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3928
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I0e23f1529b26c36d749bf5211ee8623744d0b10f
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3927
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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Implement GICD_IIDR, GICC_IIDR, GICD_PIDR0, GICD_PIDR1, GICD_PIDR2,
and GICD_PIDR3.
Change-Id: I4f6b5a6303907226e7d8e2f677543b3868c02e7b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3961
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The bootloader arguments were previously defaulting to a predetermined
value even if initialized elsewhere in the platform config script.
This commit fixes this issue by not calling the default initialization
routine if the bootloader is already defined.
Change-Id: Id80af4762b52dc036da29430b2795bb30970a349
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3967
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OnIdle() is never called since DMA active check is completely
opposite to what it should be. old active status should be 'true'
and new active status should be false for OnIdle to be called
Change-Id: I94eca50edbe96113190837c7f6e50a0d061158a6
Reported-by: Rohit Kurup <rohit.kurup@arm.com>
Signed-off-by: Rohit Kurup <rohit.kurup@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3966
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
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With the change we explicitly update the types for the VirtIO bit
masks to be Addr (uint64_t). By changing this, we ensure type
promotion where it is needed. Therefore, this fixes issues where, in
certain situations, address calculations were performed in 32-bits,
resulting in overflows.
Change-Id: I5c5c3f9a3f94e806812282da01268e18ae0d2d39
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3968
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If an interrupt was pending according to Kvm state during a drain,
the Pl390 model would create an interrupt event that could not be
serviced, preventing the system from draining. The proper behavior
is for the Pl390 not actively being used for simulation to just skip
the GIC state machine that delivers interrupts.
Change-Id: Icb37e7e992f1fb441a9b3a26daa1bb5a6fe19228
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3661
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The timer device exposed via the ARM ISA, also known as the
"CP15 timer" due to its legacy coprocessor encodings, is
implemented by the GenericTimerISA class. During Kvm
execution, however, this functionality is directly emulated
by the hardware.
This commit subclasses the GenericTimer, which is (solely)
used by GenericTimerISA, to facilitate Kvm in much the same
way as the prior GIC changes: the gem5 model is used as the
backing store for state, so checkpointing and CPU switching
work correctly, but isn't used during Kvm execution.
The added indirection prevents the timer device from creating
events when we're just updating its state, but not actually
using it for simulation.
Change-Id: I427540d11ccf049c334afe318f575146aa888672
Reviewed-on: https://gem5-review.googlesource.com/3542
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Having timer events stored in checkpoints complicates Kvm
execution. We change the timer behavior so that it always
deschedules any pending events on a drain() and recreates
them on a drainResume(), thus they will never appear in
checkpoints henceforth. This pattern of behavior makes
it simpler to handle Kvm execution, where the hardware
performs the timer function directly.
Change-Id: Ia218868c69350d96e923c640634d492b5c19cd3f
Reviewed-on: https://gem5-review.googlesource.com/3541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I3395e64311f6aa7bbfb6eee9bfec82e832bcbd4d
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3901
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I864b5d9ed655cc52e440e2eb54987e8ff9a73296
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3900
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I6b03cc6f67e76dffb79940431711ae6171901c6a
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3748
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I08de5f72513645d1fe92bde99fa205dde897e951
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3747
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I953521572e6ace475b656369c9f07ddfa50d731a
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3263
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I6d8a5e3795291b2a4cce022f555cf4b04f997538
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3262
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This commit adds support for diod to use a unix socket, rather
than a TCP port. We don't rely on the IP-based connection as we
directly use pipes to interact with diod. This allows it to work
on any system, even if the specific port is taken by another diod
instance (or similar). Secondly, the Unix socket could in theory
be used to debug. However, this functionality has not been
tested.
Change-Id: I616e0ad8768da1dfc867de3af98cdfbb22a72d63
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2820
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: Iac3d15719b2bbc426020a27d6b47a4baaab078c7
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2907
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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When it comes time to send a packet with the i8254xGBe model hooked up to
EtherTap and while running in KVM mode, the packet will first go to the
EtherTap over the network style port between them. EtherTap, because it's
not actually a model of anything in the simulation, will immediately pass
the packet off to the real network and report that the transmission was
successful to the i8254xGBe. The i8254xGBe will notice that it still has
stuff it can send (the KVM mode CPU has no trouble keeping it full) and
will, without returning and collapsing the stack, immediately call back
into EtherTap with the next packet. This loop repeats, continually
deepening the stack, until gem5 crashes with a segfault.
To break this loop, a few small changes have been made. First, txFifoTick
has been repurposed slightly so that it continuously keeps track of
whether there's still work to do to flush out the fifo during the current
tick. The code in txWire has been adjusted slightly so that it clears that
variable at the start (also removing some redundancy), so that other code
can set it again if more work needs to be done. Specifically, the
ethTxDone function will set that flag.
If there's more work to be done flushing the Fifo while in tick(), it
will loop until txFifoTick stays cleared, meaning either the Fifo is
empty, or the object on the other end hasn't said it's done yet.
Finally, a new bool member called inTick has been added which keeps track
of whether the tick() function is still active somewhere in the callstack.
If it is, then the tick event shouldn't be rescheduled in ethTxDone, since
tick will take care of that before it returns. It won't check to see if it
needs to, and so without this check there's a panic from scheduling the
same event twice.
It's not completely clear that the Fifo should send packets over and over
as fast as the other side accepts them within the same tick, although it's
not clear that it shouldn't either. If not, then probably all that would
need to change would be to remove the "while" loop so that the tick event
would be rescheduled, and the Fifo would be further emptied the next time
around.
Change-Id: I653379b43389d0539ecfadb3fc6c40e38a8864c2
Reviewed-on: https://gem5-review.googlesource.com/3642
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Fix load_addr_mask in VExpress_GEM5_V1 in order to boot with the 64-bit
kernel.
Change-Id: I13a0a752c60e53262a245cb24b16606071041397
Reviewed-on: https://gem5-review.googlesource.com/3643
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The object is called EtherTap (as opposed to EtherTapStub, what the former
EtherTap was renamed to), and its existance is gated on the linux/if_tun.h
header file existing. That's probably overly strict, but it will hopefully
be minimally likely to break the build for other systems.
Change-Id: Ie03507fadf0d843a4d4d52f283c44a416c6f2a74
Reviewed-on: https://gem5-review.googlesource.com/3646
Reviewed-by: Nathan Binkert <nate@binkert.org>
Maintainer: Nathan Binkert <nate@binkert.org>
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A lot of the implementation of EtherTapStub can be shared with a version
which uses a tap device directly. This change factors out those parts to
accommodate that.
Change-Id: I9c2e31f1be139ca73859a83f05457cef90101006
Reviewed-on: https://gem5-review.googlesource.com/3645
Reviewed-by: Nathan Binkert <nate@binkert.org>
Maintainer: Nathan Binkert <nate@binkert.org>
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The EtherTap object is going to be reworked so that it connects to a tap
device directly, but it's worthwhile to still be able to use the m5tap
utility (util/tap) to send/receive packets on systems which don't support
tap but do support the pcap API. It can also be used to replay ethernet
frames, to capture the ethernet frames coming from gem5 for analysis, to
programmatically consume and/or generate the frames, or even to forward
them to/from a remote system.
Change-Id: Ic7bd763d86cd913ac373dd10a8d6d1fc6b35f95a
Reviewed-on: https://gem5-review.googlesource.com/3644
Reviewed-by: Nathan Binkert <nate@binkert.org>
Maintainer: Nathan Binkert <nate@binkert.org>
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There needs to be a SlavePort called "tap" for the ethertap device to be
able to connect to the gem5 network successfully.
Change-Id: I1ad81219f612fd1ec278c6148af728d20bc916da
Reviewed-on: https://gem5-review.googlesource.com/3580
Reviewed-by: Nathan Binkert <nate@binkert.org>
Maintainer: Nathan Binkert <nate@binkert.org>
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Change-Id: I31808b6d7ca2bc2af41deaec747e3a13bd4f77d2
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3261
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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We don't implement the GICD_IGROUPRn registers, which is allowed, but
to be correct, they should be RAZ/WI (read as zero, writes ignored).
Change-Id: I8039baf72f45c0095f41e165b8e327c79b1ac082
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2620
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Allocate 0x10010000-0x1001ffff for m5 pseudo-ops. This range is a part
of the CS5 address range in the RS1/RS2 memory map.
Change-Id: Ica45cd53bc4ebb62966afa099fa465e27fb0452c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2965
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