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2014-10-01arm: More UBSan cleanups after additional full-system runsAndreas Hansson
Some incorrect casting to IntRegIndex, and a few uninitialized members in the i8254xGBe device.
2014-09-27dev: Output invalid access size in IsaFake panicCurtis Dunham
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh
2014-07-25energy: Add the Energy Controller in the right configsStephan Diestelhorst
Tie in the newly created energy controller components in the default configurations.
2014-09-20energy: Memory-mapped Energy Controller componentAkash Bagdia
This patch provides an Energy Controller device that provides software (driver) access to a DVFS handler. The device is currently residing in the dev/arm tree, but there is nothing inherently ARM specific in the behaviour. It is currently only tested and supported for ARM Linux, hence the location.
2014-09-20dev: Add support for 9p proxying over VirtIOAndreas Sandberg
This patch adds support for 9p filesystem proxying over VirtIO. It can currently operate by connecting to a 9p server over a socket (VirtIO9PSocket) or by starting the diod 9p server and connecting over pipe (VirtIO9PDiod). *WARNING*: Checkpoints are currently not supported for systems with 9p proxies!
2014-09-20dev: Add a VirtIO block device modelAndreas Sandberg
2014-09-20dev: Add a VirtIO console device modelAndreas Sandberg
2014-09-20dev, pci: Implement basic VirtIO supportAndreas Sandberg
This patch adds support for VirtIO over the PCI bus. It does so by providing the following new SimObjects: * VirtIODeviceBase - Abstract base class for VirtIO devices. * PciVirtIO - VirtIO PCI transport interface. A VirtIO device is hooked up to the guest system by adding a PciVirtIO device to the PCI bus and connecting it to a VirtIO device using the vio parameter. New VirtIO devices should inherit from VirtIODevice base and implementing one or more VirtQueues. The VirtQueues are usually device-specific and all derive from the VirtQueue class. Queues must be registered with the base class from the constructor since the device assumes that the number of queues stay constant.
2014-09-20dev: Refactor terminal<->UART interface to make it more genericAndreas Sandberg
The terminal currently assumes that the transport to the guest always inherits from the Uart class. This assumption breaks when implementing, for example, a VirtIO consoles. This patch removes this assumption by adding pointer to the from the terminal to the uart and replacing it with a more general callback interface. The Uart, or any other class using the terminal, class implements an instance of the callbacks class and registers it with the terminal.
2014-09-20base: Clean up redundant string functions and use C++11Andreas Hansson
This patch does a bit of housekeeping on the string helper functions and relies on the C++11 standard library where possible. It also does away with our custom string hash as an implementation is already part of the standard library.
2014-09-12style: Fix line continuation, especially in debug messagesAndrew Bardsley
This patch closes a number of space gaps in debug messages caused by the incorrect use of line continuation within strings. (There's also one consistency change to a similar, but correct, use of line continuation)
2014-09-03dev: seperate legacy io offsets from PCI offsetAli Saidi
The PC platform has a single IO range that is used both legacy IO and PCI IO while other platforms may use seperate regions. Provide another mechanism to configure the legacy IO base address range and set it to the PCI IO address range for x86.
2014-09-03arm: Support >2GB of memory for AArch64 systemsAli Saidi
2014-09-03dev, arm: Add support for linux generic pci host driverAli Saidi
This change adds support for a generic pci host bus driver that has been included in recent Linux kernel instead of the more bespoke one we've been using to date. It also works with aarch64 so it provides PCI support for 64-bit ARM Linux. To make this work a new configuration option pci_io_base is added to the RealView platform that should be set to the start of the memory used as memory mapped IO ports (IO ports that are memory mapped, not regular memory mapped IO). And a parameter pci_cfg_gen_offsets which specifies if the config space offsets should be used that the generic driver expects. To use the pci-host-generic device you need to: pci_io_base = 0x2f000000 (Valid for VExpress EMM) pci_cfg_gen_offsets = True and add the following to your device tree: pci { compatible = "pci-host-ecam-generic"; device_type = "pci"; #address-cells = <0x3>; #size-cells = <0x2>; #interrupt-cells = <0x1>; //bus-range = <0x0 0x1>; // CPU_PHYSICAL(2) SIZE(2) // Note, some DTS blobs only support 1 size reg = <0x0 0x30000000 0x0 0x10000000>; // IO (1), no bus address (2), cpu address (2), size (2) // MMIO (1), at address (2), cpu address (2), size (2) ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x10000>, <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x10000000>; // With gem5 we typically use INTA/B/C/D one per device interrupt-map = <0x0000 0x0 0x0 0x1 0x1 0x0 0x11 0x1 0x0000 0x0 0x0 0x2 0x1 0x0 0x12 0x1 0x0000 0x0 0x0 0x3 0x1 0x0 0x13 0x1 0x0000 0x0 0x0 0x4 0x1 0x0 0x14 0x1>; // Only match INTA/B/C/D and not BDF interrupt-map-mask = <0x0000 0x0 0x0 0x7>; };
2014-09-03config: Refactor RealviewEMM to fit into new config systemGeoffrey Blake
This eliminates some default devices and adds in helper functions to connect the devices defined here to associate with the proper clock domains.
2014-09-03dev: Avoid invalid sized reads in PL390 with DPRINTF enabledMitch Hayenga
The first DPRINTF() in PL390::writeDistributor always read a uint32_t, though a packet may have only been 1 or 2 bytes. This caused an assertion in packet->get().
2014-08-13mips: Remove unused private members to fix compile-time warningAndreas Sandberg
Certain versions of clang complain about unused private members if they are not used. This changeset removes such members from the MIPS-specific classes to silence the warning.
2014-07-18x86: make PioBus return BadAddress errorsBinh Pham
Stop setting the use_default_range flag in PioBus in order to have random bad addresses result in a BadAddress response and not a gem5 fatal error. This is necessary in Ruby as Ruby is connected directly to PioBus, so misspeculated addresses will be sent there directly. For the classic memory system, this change has no effect, as bad addresses are caught by the memory bus before being sent to the PioBus. This work was done while Binh was an intern at AMD Research.
2014-05-09dev: Set HDLCD default pixel clock for 1080p @ 60HzChris Emmons
This patch changes the default pixel clock to effectively generate 1080p resolution at 60 frames per second. It is dependent upon the kernel device tree file using the specified resolution / display string in the comments.
2014-05-09arm: quick hack to allow a greater number of CPUs to a guest OSMatt Evans
This is a quick hack to communicate a greater number of CPUs to a guest OS via the ARM A9 SCU config register. Some OSes (Linux) just look at the bottom field to count CPUs and with a small change can look at bits [3:0] to learn about up to 16 CPUs. Very much unsupported (and contains warning messages as such) but useful for running 8 core sims without hardwiring CPU count in the guest OS.
2014-04-09dev: Protect PollEvent processing when running in parallel modeAndreas Sandberg
The calling thread is undefined when the PollQueue services events. This implies that PollEvents need to handle the case where they are processed from a different thread than the thread that created the event. This changeset adds temporary event queue migrations to the VNC server, the ethernet tap device, and the terminal to protect them from inter-thread calls.
2014-03-23dev: Fix IsaFake's cxx_header settingAndrew Bardsley
cxx_header was set incorrectly on IsaFake
2014-02-18dev: Include basic devices in NULL ISA buildAndreas Hansson
This patch enbles use of the basic PIO devices as part of the NULL build. Although it might seem counter intuitive to have a PIO device without being able to execute a driver, this change enables us to break a device class hierarchy into an ISA-agnostic part, and an ISA-specific part, without requiring multiple-inheritance. The ISA-agnostic base class is a PIO device, but does not make use of the port.
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
This patch enables tracking of cache occupancy per thread along with ages (in buckets) per cache blocks. Cache occupancy stats are recalculated on each stat dump.
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
This patch adds support for simulating with multiple threads, each of which operates on an event queue. Each sim object specifies which eventq is would like to be on. A custom barrier implementation is being added using which eventqs synchronize. The patch was tested in two different configurations: 1. ruby_network_test.py: in this simulation L1 cache controllers receive requests from the cpu. The requests are replied to immediately without any communication taking place with any other level. 2. twosys-tsunami-simple-atomic: this configuration simulates a client-server system which are connected by an ethernet link. We still lack the ability to communicate using message buffers or ports. But other things like simulation start and end, synchronizing after every quantum are working. Committed by: Nilay Vaish
2013-10-31dev: Add 'OSC' oscillator sys control reg support to VersatileExpressMatt Evans
The VE motherboard provides a set of system control registers through which various motherboard and coretile registers are accessed. Voltage regulators and oscillator (DLL/PLL) config are examples. These registers must be impleted to boot Linux 3.9+ kernels.
2013-10-31dev: Add support for MSI-X and Capability Lists for ARM and PCI devicesGeoffrey Blake
This patch adds the registers and fields to the PCI device to support Capability lists and to support MSI-X in the GIC.
2013-10-31dev: Fix race conditions in IDE device on newer kernelsGeoffrey Blake
Newer linux kernels and distros exercise more functionality in the IDE device than previously, exposing 2 races. The first race is the handling of aborted DMA commands would immediately report the device is ready back to the kernel and cause already in flight commands to assert the simulator when they returned and discovered an inconsitent device state. The second race was due to the Status register not being handled correctly, the interrupt status bit would get stuck at 1 and the driver eventually views this as a bad state and logs the condition to the terminal. This patch fixes these two conditions by making the device handle aborted commands gracefully and properly handles clearing the interrupt status bit in the Status register.
2013-10-17arm: Add a 'clear PPI' method to gic_pl390Matt Evans
The underlying assumption that all PPIs must be edge-triggered is strained when the architected timers and VGIC interfaces make level-behaviour observable. For example, a virtual timer interrupt 'goes away' when the hypervisor is entered and the vtimer is disabled; this requires a PPI to be de-activated. The new method simply clears the interrupt pending state.
2013-10-17dev: Add option to disable framebuffer .bmp dump in run folderDam Sunwoo
There is an option to enable/disable all framebuffer dumps, but the last frame always gets dumped in the run folder with no other way to disable it. These files can add up very quickly running many experiments. This patch adds an option to disable them. The default behavior remains unchanged.
2013-10-17arm: Fix a GIC mask register bugAli Saidi
This resulted in a kernel printk that said, "GIC CPU mask not found - kernel will fail to boot."
2013-10-17dev: Allow additional UART interrupts to be setAli Saidi
This patch allows setting a few additional interrupts for status changes that should never occur.
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. --HG-- rename : build_opts/NOISA => build_opts/NULL rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
2013-09-04arch: Header clean up for NOISA resurrectionAndreas Hansson
This patch is a first step to getting NOISA working again. A number of redundant includes make life more difficult than it has to be and this patch simply removes them. There are also some redundant forward declarations removed.
2013-08-19mem: Change AbstractMemory defaults to match the common caseAndreas Hansson
This patch changes the default parameter value of conf_table_reported to match the common case. It also simplifies the regression and config scripts to reflect this change.
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
This patch removes the notion of a peer block size and instead sets the cache line size on the system level. Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used. A follow-on patch updates the configuration scripts accordingly.
2013-07-11dev: make BasicPioDevice take size in constructorSteve Reinhardt
Instead of relying on derived classes explicitly assigning to the BasicPioDevice pioSize field, require them to pass a size value in to the constructor. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-07-11dev: consistently end device classes in 'Device'Steve Reinhardt
PciDev and IntDev stuck out as the only device classes that ended in 'Dev' rather than 'Device'. This patch takes care of that inconsistency. Note that you may need to delete pre-existing files matching build/*/python/m5/internal/param_* as scons does not pick up indirect dependencies on imported python modules when generating params, and the PciDev -> PciDevice rename takes place in a file (dev/Device.py) that gets imported quite a bit. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-07-11dev/arm: get rid of AmbaDev namespaceSteve Reinhardt
It was confusing having an AmbaDev namespace along with an AmbaDevice class. The namespace stuff is now moved in to a new base AmbaDevice class, which is a mixin for classes AmbaPioDevice (the former AmbaDevice) and AmbaDmaDevice to provide the readId function as an inherited member function. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-07-11devices: make more classes derive from BasicPioDeviceSteve Reinhardt
A couple of devices that have single fixed memory mapped regions were not derived from BasicPioDevice, when that's exactly the functionality that BasicPioDevice provides. This patch gets rid of a little bit of redundant code by making those devices actually do so. Also fixed the weird case of X86ISA::Interrupts, where the class already did derive from BasicPioDevice but didn't actually use all the features it could have. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
This patch adds the notion of source- and derived-clock domains to the ClockedObjects. As such, all clock information is moved to the clock domain, and the ClockedObjects are grouped into domains. The clock domains are either source domains, with a specific clock period, or derived domains that have a parent domain and a divider (potentially chained). For piece of logic that runs at a derived clock (a ratio of the clock its parent is running at) the necessary derived clock domain is created from its corresponding parent clock domain. For now, the derived clock domain only supports a divider, thus ensuring a lower speed compared to its parent. Multiplier functionality implies a PLL logic that has not been modelled yet (create a separate clock instead). The clock domains should be used as a mechanism to provide a controllable clock source that affects clock for every clocked object lying beneath it. The clock of the domain can (in a future patch) be controlled by a handler responsible for dynamic frequency scaling of the respective clock domains. All the config scripts have been retro-fitted with clock domains. For the System a default SrcClockDomain is created. For CPUs that run at a different speed than the system, there is a seperate clock domain created. This domain incorporates the CPU and the associated caches. As before, Ruby runs under its own clock domain. The clock period of all domains are pre-computed, such that no virtual functions or multiplications are needed when calling clockPeriod. Instead, the clock period is pre-computed when any changes occur. For this to be possible, each clock domain tracks its children.
2013-06-27config: Remove redundant explicit setting of default clocksAkash Bagdia
This patch removes the explicit setting of the clock period for certain instances of CoherentBus, NonCoherentBus and IOCache where the specified clock is same as the default value of the system clock. As all the values used are the defaults, there are no performance changes. There are similar cases where the toL2Bus is set to use the parent CPU clock which is already the default behaviour. The main motivation for these simplifications is to ease the introduction of clock domains.
2013-06-04dev: Clarify why updates are delayed when the MC14818 is activatedAndreas Sandberg
2013-06-03dev: Add support for disabling ticking and the divider in MC146818Andreas Sandberg
Some Linux versions disable updates (regB.set = 1) to prevent the chip from updating its internal state while the OS is updating it. Support for this was already there, this patch merely disables the check in writeReg that prevented it from being enabled. The patch also includes support for disabling the divider, which is used to control when clock updates should start after setting the internal RTC state. These changes are required to boot most vanilla Linux distributions that update the RTC settings at boot.
2013-06-03dev: Clean up MC146818 register (A & B) handlingAndreas Sandberg
Rewrite reg A & B handling to use the bitunion stuff instead of bit masking. Add better error messages when the kernel tries to enable unsupported stuff.
2013-05-30mem: Avoid explicitly zeroing the memory backing storeAndreas Hansson
This patch removes the explicit memset as it is redundant and causes the simulator to touch the entire space, forcing the host system to allocate the pages. Anonymous pages are mapped on the first access, and the page-fault handler is responsible for zeroing them. Thus, the pages are still zeroed, but we avoid touching the entire allocated space which enables us to use much larger memory sizes as long as not all the memory is actually used.
2013-04-22sim: separate nextCycle() and clockEdge() in clockedObjectsDam Sunwoo
Previously, nextCycle() could return the *current* cycle if the current tick was already aligned with the clock edge. This behavior is not only confusing (not quite what the function name implies), but also caused problems in the drainResume() function. When exiting/re-entering the sim loop (e.g., to take checkpoints), the CPUs will drain and resume. Due to the previous behavior of nextCycle(), the CPU tick events were being rescheduled in the same ticks that were already processed before draining. This caused divergence from runs that did not exit/re-entered the sim loop. (Initially a cycle difference, but a significant impact later on.) This patch separates out the two behaviors (nextCycle() and clockEdge()), uses nextCycle() in drainResume, and uses clockEdge() everywhere else. Nothing (other than name) should change except for the drainResume timing.
2013-04-22ARM: Add support for HDLCD controller for TC2 and newer Versatile Express tiles.Chris Emmons
Newer core tiles / daughterboards for the Versatile Express platform have an HDLCD controller that supports HD-quality output. This patch adds an implementation of the controller.