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2017-04-03arm, dev: add basic support for GICC_BPR registerCurtis Dunham
The Binary Point Register (BPR) specifies which bits belong to the group priority field (which are used for preemption) and which to the subpriority field (which are ignored for preemption). Change-Id: If51e669d23b49047b69b82ab363dd01a936cc93b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2443 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handlingCurtis Dunham
The aforementioned registers (Interrupt Processor Targets Registers) are banked per-CPU, but are read-only. This patch eliminates the per-CPU storage of these values that are simply computed. Change-Id: I52cafc2f58e87dd54239a71326c01f4923544689 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2442 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm: refactor packet processing in Pl390 GICCurtis Dunham
Change-Id: I696703418506522ba90df5c2c4ca45c95a6efbea Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2441 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03dev, arm: Fix multi-core KVM race in the generic timerAndreas Sandberg
The generic timer sometimes needs to access global state. This can lead to race conditions when simulating a multi-core KVM system where each core lives in its own thread. In that case, the setMiscReg and readMiscReg methods are called from the thread owning the CPU and not the global device thread. Change-Id: Ie3e982258648c8562cce0b30a0c122dfbfaf42cd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2460 Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03dev: Align BAR0 size to power of 2 for VirtIO devicesSascha Bischoff
When setting the size of a PCI BAR, the kernel only supports powers of two (as per the PCI spec). Previously, the size was incorrectly read by the kernel, and the address ranges assigned to the PCI devices could overlap, resulting in gem5 crashes. We now round up to the next power of two. Kudos to Sergei Trofimov who helped to debug this issue! Change-Id: I54ca399b62ea07c09d4cd989b17dfa670e841bbe Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-by: Sergei Trofimov <sergei.trofimov@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2580 Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
2017-04-03dev: Add a dummy VirtIO deviceAndreas Sandberg
VirtIO transport interfaces always expect a VirtIO device pointer. However, there are cases (in particular when using VirtIO's MMIO interface) where we want to instantiate an interface without a device. Add a dummy device using VirtIO device ID 0 and no queues to handle this use case. Change-Id: I6cbe12fd403903ef585be40279c3b1321fde48ff Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2325 Reviewed-by: Weiping Liao <weipingliao@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-03dev: Rename VirtIO PCI debug flagAndreas Sandberg
Rename VIOPci -> VIOIface to avoid having a separate flag for the MMIO interface. Change-Id: I99f9210fa36ce33662c48537fd3992cd9a69d349 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2324 Reviewed-by: Weiping Liao <weipingliao@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-21arm: correct register read bug in Pl390 GICCurtis Dunham
Change-Id: I4c0de7c2a5b40c1a9f009ca12062cb108b450b04 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-15arm, dev: Add missing override in the Pl390 GIC modelAndreas Sandberg
The Pl390::getAddrRanges() method should have been flagged using the override keyword. Other methods in this class already use the override keyword, so this results in a warning about inconsistent override usage when compiling using clang. Change-Id: I17449687a8e074262232562487b58c96466bd54e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-03-13dev, arm: Add draining to the GIC modelAndreas Sandberg
The GIC model currently adds a delay to interrupts when posting them to a target CPU. This means that an interrupt signal will be represented by an event for a short period of time. We currently ignore this when draining and serialize the tick when the interrupt will fire. Upon loading the checkpoint, the simulated GIC reschedules the pending events. This behaviour is undesirable when we implement support for switching between in-kernel GIC emulation and gem5 GIC emulation. In that case, the (kernel) GIC model gets a lot simpler if we don't need to worry about in-flight interrupts from the gem5 GIC. This changeset adds a draining check to force the GIC into a state where all interrupts have been delivered prior to checkpointing/CPU switching. It also removes the now redundant serialization of interrupt events. Change-Id: I8b8b080aa291ca029a3a7bdd1777f1fcd5b01179 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2331 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-13arm: Clean up the GIC implementationAndreas Sandberg
Lots of minor cleaups: * Make cached params const * Don't serialize params * Use AddrRange to represent the distributor and CPU address spaces * Store a const AddrRangeList of all PIO ranges Change-Id: I40a17bc3a38868fb3b8af247790e852cf99ddf1d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2330 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-07dev, arm: Render HDLCD frames at a fixed rate in KVMSudhanshu Jha
Use the new fast scan-out API in the PixelPump to render frames at a fixed frame rate in KVM mode. The refresh rate when running in KVM can be controlled by the virt_refresh_rate parameter. Change-Id: Ib3c78f174e3f8f4ca8a9b723c4e5d311a433b8aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2242 Reviewed-by: Rahul Thakur <rjthakur@google.com>
2017-03-07dev: Add support for single-pass scan out in the PixelPumpSudhanshu Jha
Add a helper function to scan out an entire frame in one time step. This requires the public PixelPump to be changed somewhat to separate timing updates from general PixelPump control. Instead of calling PixelPump::start(timings), timings now need to be updated using a separate call to PixelPump::updateTimings(timings) before calling PixelPump::start(). Display controllers that don't need accurate timing (e.g., in KVM mode), can use the new PixelPump::renderFrame() API to render an entire frame in one step. This call results in the same callbacks (e.g., calls to nextPixel()) as the timing calls, but they all happen in immediately. Unlike the timing counterpart, renderFrame() doesn't support buffer underruns and will panic if nextPixle() indicates an underrun. Change-Id: I76c84db04249b02d4207c5281d82aa693d0881be Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2241 Reviewed-by: Rahul Thakur <rjthakur@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-07dev, kvm: Add a fast KVM-aware mode in DmaReadFifoSudhanshu Jha
Use a fast, functional, read operations keep the DMA FIFO full when running in KVM mode. Change-Id: I5b378c2fb6a1d3e687cef15e807e63a0a53a60e2 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2226 Reviewed-by: Rahul Thakur <rjthakur@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-03-07arm, kmi: Clear interrupts in KMI devicesSudhanshu Jha
Added functionality to check and clear interrupts for KMI devices. This fixes a boot bug when using KVM and in-kernel GIC emulation. Change-Id: Ia3e91d07567b7faf3f82b0adfda4a165a502a339 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2225 Reviewed-by: Rahul Thakur <rjthakur@google.com>
2017-02-14arm, kvm: Automatically use the MuxingKvmGicAndreas Sandberg
Automatically use the MuxingKvmGic in the VExpress_GEM5_V1 platform. This removes the need to patch the host kernel or the platform configuration when using KVM on ARM. Change-Id: Ib1ed9b3b849b80c449ef1b62b83748f3f54ada26 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2017-02-14sim,kvm,arm: fix typosCurtis Dunham
Change-Id: Ifc65d42eebfd109c1c622c82c3c3b3e523819e85 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-02-09dev: net/i8254xGBe add two more wakeup registers to ignoreBjoern A. Zeeb
There are drivers writing to WUFC uncondtionally of anything. In order to not panic gem5 in these cases, ignore writes to WUFC and WUS as we do for WUC. Similarly return 0 (default reset value) on reads. Testing Done: Booted in FS with such a driver revision which would previously panic and now boots fine. Reviewed at http://reviews.gem5.org/r/3791/ Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2016-11-09style: [patch 3/22] reduce include dependencies in some headersBrandon Potter
Used cppclean to help identify useless includes and removed them. This involved erroneously included headers, but also cases where forward declarations could have been used rather than a full include.
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-12-19dev: Include DmaDevice in NULL buildsAndreas Sandberg
Builds for the NULL ISA include Device.py, which contains the Python declaration of DmaDevice, but don't include the actual C++ implementation. Add dma_device.cc to the NULL build to the Python and C++ worlds consistent again. Change-Id: I47a57181a1f4d5a7276467678bf16fbc7f161681 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
2016-12-19python: Fix incorrect header in the DmaDevice wrapperAndreas Sandberg
The header declared in the DmaDevice wrapper doesn't actually contain the DmaDevice class. This can potentially lead to incorrect type cases in Swig. Change-Id: If2266d4180d1d6fd13359a81067068854c5e96fe Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
2016-12-06dev: Fix race conditions at terminating dist-gem5 simulationsGabor Dozsa
Two problems may arise when a distributed gem5 simulation terminates: (i) simulation thread(s) may get stuck in an incomplete synchronisation event which prohibits processing the simulation exit event; and (ii) a stale receiver thread may try to access objects that have already been deleted while exiting gem5. This patch terminates receive threads properly and aborts the processing of any incomplete synchronisation event. Change-Id: I72337aa12c7926cece00309640d478b61e55a429 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-11-29dev: Fix buffer length when unserializing an eth pktMichael LeBeane
Changeset 11701 only serialized the useful portion of of an ethernet packets' payload. However, the device models expect each ethernet packet to contain a 16KB buffer, even if there is no data in it. This patch adds a 'bufLength' field to EthPacketData so the original size of the packet buffer can always be unserialized. Reported-by: Gabor Dozsa <Gabor.Dozsa@arm.com>
2016-10-26dev: Add m5 op to toggle synchronization for dist-gem5.Michael LeBeane
This patch adds the ability for an application to request dist-gem5 to begin/ end synchronization using an m5 op. When toggling on sync, all nodes agree on the next sync point based on the maximum of all nodes' ticks. CPUs are suspended until the sync point to avoid sending network messages until sync has been enabled. Toggling off sync acts like a global execution barrier, where all CPUs are disabled until every node reaches the toggle off point. This avoids tricky situations such as one node hitting a toggle off followed by a toggle on before the other nodes hit the first toggle off.
2016-10-26dev: Add 'simLength' parameter in EthPacketDatamlebeane
Currently, all the network devices create a 16K buffer for the 'data' field in EthPacketData, and use 'length' to keep track of the size of the packet in the buffer. This patch introduces the 'simLength' parameter to EthPacketData, which is used to hold the effective length of the packet used for all timing calulations in the simulator. Serialization is performed using only the useful data in the packet ('length') and not necessarily the entire original buffer.
2016-10-15arm, dev: pl011 console interactivityBjoern A. Zeeb
Improve PL011 console interactivity Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2016-10-07dev, arm: Make GenericTimer param handling more robustAndreas Sandberg
The generic timer needs a pointer to an ArmSystem to wire itself to the system register handler. This was previously specified as an instance of System that was later cast to ArmSystem. Make this more robust by specifying it as an ArmSystem in the Python interface and add a check to make sure that it is non-NULL. Change-Id: I989455e666f4ea324df28124edbbadfd094b0d02 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-09-22arm: disable GIC extensionsCurtis Dunham
Change-Id: If19b9c593b48ded1ea848f2d3710d4369ec8a221 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-09-13dev: Add a DmaCallback class to DmaDeviceMichael LeBeane
This patch introduces the DmaCallback helper class, which registers a callback to fire after a sequence of (potentially non-contiguous) DMA transfers on a DmaPort completes.
2016-09-13dev: Exit correctly in dist-gem5Michael LeBeane
The receiver thread in dist_iface is allowed to directly exit the simulation. This can cause exit to be called twice if the main thread simultaneously wants to exit the simulation. Therefore, have the receiver thread enqueue a request to exit on the primary event queue for the main simulation thread to handle.
2016-09-06dev, arm: Add a customizable NoMali GPU modelAndreas Sandberg
Add a customizable NoMali GPU model and an example Mali T760 configuration. Unlike the normal NoMali model (NoMaliGpu), the NoMaliCustopmGpu model exposes all the important GPU ID registers to Python. This makes it possible to implement custom GPU configurations by without changing the underlying NoMali library. Change-Id: I4fdba05844c3589893aa1a4c11dc376ec33d4e9e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
2016-08-16dev: Revert 0a316996de76 [dev, sim: Added missing override...]Andreas Sandberg
This changeset reverts the changset "dev, sim: Added missing override keywords to fix CLANG compilation (OSX)" which was incorrectly rebased. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-15dev, sim: Added missing override keywords to fix CLANG compilation (OSX)Matteo Andreozzi
Change-Id: Ice5fa11e77d06576eaa42149f5fa340a769d8b01 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-10arm, dev: Add support for listing DMA ports in new platformsAndreas Sandberg
When using a Ruby memory system, the Ruby configuration scripts expect to get a list of DMA ports to create the necessary DMA sequencers. Add support in the utility functions that wire up devices to append DMA ports to a list instead of connecting them to the IO bus. These functions are currently only used by the VExpress_GEM5_V1 platform. Change-Id: I46059e46b0f69e7be5f267e396811bd3caa3ed63 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
2016-08-10arm: Don't report the boot ROM as a memory in config tablesAndreas Sandberg
The boot ROM shouldn't be used as a memory by the kernel. Memories have a flag to indicate this which is set for some platforms. Update all platforms to consistently set this flag to indicate that the boot ROM shouldn't be reported as normal memory. Change-Id: I2bf0273e99d2a668e4e8d59f535c1910c745aa7b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com> --HG-- extra : amend_source : c2cbda38636ea37cbe9ae6977a06b923eab5ba56
2016-08-02arm: s/ctx_id/ctx/ the GICCurtis Dunham
Factored out of the larger banked register change. Change-Id: I947dbdb9c00b4678bea9d4f77b913b7014208690 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-02arm: bank GIC registers per CPUCurtis Dunham
Updated according to GICv2 documentation. Change-Id: I5d926d1abf665eecc43ff0f7d6e561e1ee1c390a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-07-19dev, dist: Fixed a scheduling bug in the etherswitchMohammad Alian
This patch fixes a bug in etherswitch. When a packet gets inserted in the output fifo, the txEvent has to always be reschedule, not only when an event is already scheduled. This can raise the assertion in the reschedule function.
2016-06-08dist, dev: Fixed the packet ordering in etherswitchMohammad Alian
This patch fixes the order that packets gets pushed into the output fifo of etherswitch. If two packets arrive at the same tick to the etherswitch, we sort and push them based on their source port id. In dist-gem5 simulations, if there is no ordering inforced while two packets arrive at the same tick, it can lead to non-deterministic simulations Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-06-06stats: Fixing regStats function for some SimObjectsDavid Guillen Fandos
Fixing an issue with regStats not calling the parent class method for most SimObjects in Gem5. This causes issues if one adds new stats in the base class (since they are never initialized properly!). Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
We want to extend the stats of objects hierarchically and thus it is necessary to register the statistics of the base-class(es), as well. For now, these are empty, but generic stats will be added there. Patch originally provided by Akash Bagdia at ARM Ltd.
2016-05-26dev, arm: Add a flag to enable/disable gem5 GIC extensionsAndreas Sandberg
Make it possible to disable gem5 gic extensions by setting the gem5_extensions param to False from Python. Change-Id: Icb255105925ef49891d69cc9fe5cc55578ca066d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Geoffrey Blake <geoffrey.blake@arm.com>
2016-05-26arm, dev: Remove superfluous loop increment in flash deviceAndreas Hansson
As identified by clang-3.8, there was a superfluous loop increment in the flash device which is now removed. Change-Id: If46a1c4f72d3d4c9f219124030894ca433c790af Reviewed-by: Rene De Jong <rene.dejong@arm.com>
2016-05-19arm,dev: PL011 UART_FR read status enhancementBjoern A. Zeeb
Given we do not simulate a FIFO currently there are only two states we can be in upon read: empty or full. Properly signal the latter. Add and sort constants for states in the header file. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19dev, virtio: properly set PCI address space to use IOREGBjoern A. Zeeb
VirtIO spec < 1.0 demands IOREG to be used on PCI and not memory mapped. Set the correct bit on the PCI address accordingly. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-06dev, arm: Update GIC to use GICv2 register namingAndreas Sandberg
The GICv2 has a new and slightly more consistent register naming. Update gem5's GIC register names to match the new documentation. Change-Id: I8ef114eee8a95bf0b88b37c18a18e137be78675a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-04-27dev: Fix incorrect terminal backlog handlingAndreas Sandberg
The Terminal device currently uses the peek functionality in gem5's circular buffer implementation to send existing buffered content on the terminal when a new client attaches. This functionallity is however not implemented correctly and re-sends the same block multiple time. Add the required functionality to peek with an offset into the circular buffer and change the Terminal::accept() implementation to send the buffered contents. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2016-04-12misc: Appease clang...againAndreas Hansson
Once again, clang is having issues with recently committed code. Unfortunately HSAIL_X86 is still broken.
2016-04-07Revert to 74c1e6513bd0 (sim: Thermal support for Linux)Andreas Sandberg